Abstract: In a standard cell, rise time when an output transitions from a low-level voltage to a high-level voltage and fall time when an output transitions from the high-level voltage to the low-level voltage differ from each other. A flip-flop outputs a first input signal, which is input in a cycle immediately before a clock in synchronization with one of rise and fall of the clock, to the standard cell and then fixes an output the signal at one of a high-level voltage and a low-level voltage. Before a second input signal, which is output from the flip-flop after the first input signal, reaches the standard cell, an output of the standard cell is set at one of a high-level voltage and a low-level voltage, which corresponds to a signal whose transition speed is slow, by one of the high-level voltage and the low-level voltage that is output from the flip-flop.

Abstract: There is disclosed a semiconductor integrated circuit in which an equalize circuit is connected between input nodes N1, bN1 of a differential sense amplifier. A latch circuit is connected between nodes N2, bN2. A data change circuit is connected between the nodes N1 and bN2 and between the nodes bN1 and N2. A disconnection circuit is connected between the nodes N1 and N2 and between the nodes bN1 and bN2. In a state in which potentials of the input nodes N1, bN1 are equal to each other, the differential sense amplifier is operated, and output data of the amplifier is reversed by the data change circuit and subsequently latched by the latch circuit. The latched data is supplied to the input nodes N1, bN1 of the differential sense amplifier.