Patents by Inventor Yasuhito Maki
Yasuhito Maki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8169572Abstract: A display apparatus includes: at least one pixel section including a display cell that has a pixel electrode and a light-receiving cell that has a light-receiving element; and a shielding electric conductor configured to electrically shield the pixel electrode on the side of the display cell from the light-receiving element. The shielding electric conductor is formed between the pixel electrode and the light-receiving element and has a fixed potential.Type: GrantFiled: September 26, 2007Date of Patent: May 1, 2012Assignee: Sony CorporationInventors: Go Yamanaka, Masafumi Matsui, Mitsuru Tateuchi, Yasuhito Maki, Yoshiharu Nakajima
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Patent number: 8159590Abstract: When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.Type: GrantFiled: June 17, 2009Date of Patent: April 17, 2012Assignee: Sony CorporationInventors: Satoshi Yoshihara, Yasuhito Maki
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Patent number: 7893982Abstract: When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.Type: GrantFiled: July 20, 2009Date of Patent: February 22, 2011Assignee: Sony CorporationInventors: Satoshi Yoshihara, Yasuhito Maki
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Publication number: 20090278972Abstract: When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.Type: ApplicationFiled: July 20, 2009Publication date: November 12, 2009Applicant: Sony CorporationInventors: Satoshi Yoshihara, Yasuhito Maki
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Publication number: 20090256944Abstract: When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.Type: ApplicationFiled: June 17, 2009Publication date: October 15, 2009Applicant: Sony CorporationInventors: Satoshi Yoshihara, Yasuhito Maki
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Patent number: 7589776Abstract: When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.Type: GrantFiled: November 9, 2006Date of Patent: September 15, 2009Assignee: Sony CorporationInventors: Satoshi Yoshihara, Yasuhito Maki
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Patent number: 7573521Abstract: When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.Type: GrantFiled: July 3, 2006Date of Patent: August 11, 2009Assignee: Sony CorporationInventors: Satoshi Yoshihara, Yasuhito Maki
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Patent number: 7535507Abstract: When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an ORB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.Type: GrantFiled: March 8, 2005Date of Patent: May 19, 2009Assignee: Sony CorporationInventors: Satoshi Yoshihara, Yasuhito Maki
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Patent number: 7432906Abstract: A timing generation circuit (15) is formed integrally on the same glass substrate (11) together with a display area section (12) similarly to an H driver (13U) and a V driver (14), and timing pulses to be used by the H driver (13U) and the V driver (14) are produced based on timing data produced by a shift register (31U) of the H driver (13U) and a shift register (14A) of the V driver (14). The invention thereby provides a timing generation circuit which can contribute to miniaturization and reduction of the cost of the set and a display apparatus of the active matrix type in which the timing generation circuit is incorporated.Type: GrantFiled: March 23, 2005Date of Patent: October 7, 2008Assignee: Sony CorporationInventors: Yoshiharu Nakajima, Yasuhito Maki, Toshikazu Maekawa
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Publication number: 20080084526Abstract: A display apparatus includes: at least one pixel section including a display cell that has a pixel electrode and a light-receiving cell that has a light-receiving element; and a shielding electric conductor configured to electrically shield the pixel electrode on the side of the display cell from the light-receiving element. The shielding electric conductor is formed between the pixel electrode and the light-receiving element and has a fixed potential.Type: ApplicationFiled: September 26, 2007Publication date: April 10, 2008Applicant: Sony CorporationInventors: Go Yamanaka, Masafumi Matsui, Mitsuru Tateuchi, Yasuhito Maki, Yoshiharu Nakajima
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Publication number: 20070052828Abstract: When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.Type: ApplicationFiled: November 9, 2006Publication date: March 8, 2007Applicant: Sony CorporationInventors: Satoshi Yoshihara, Yasuhito Maki
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Publication number: 20060250512Abstract: When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.Type: ApplicationFiled: July 3, 2006Publication date: November 9, 2006Inventors: Satoshi Yoshihara, Yasuhito Maki
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Patent number: 7071977Abstract: When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.Type: GrantFiled: September 20, 2002Date of Patent: July 4, 2006Assignee: Sony CorporationInventors: Satoshi Yoshihara, Yasuhito Maki
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Publication number: 20050168428Abstract: A timing generation circuit (15) is formed integrally on the same glass substrate (11) together with a display area section (12) similarly to an H driver (13U) and a V driver (14), and timing pulses to be used by the H driver (13U) and the V driver (14) are produced based on timing data produced by a shift register (31U) of the H driver (13U) and a shift register (14A) of the V driver (14). The invention thereby provides a timing generation circuit which can contribute to miniaturization and reduction of the cost of the set and a display apparatus of the active matrix type in which the timing generation circuit is incorporated.Type: ApplicationFiled: March 23, 2005Publication date: August 4, 2005Inventors: Yoshiharu Nakajima, Yasuhito Maki, Toshikazu Maekawa
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Publication number: 20050151865Abstract: When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.Type: ApplicationFiled: March 8, 2005Publication date: July 14, 2005Inventors: Satoshi Yoshihara, Yasuhito Maki
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Patent number: 6894674Abstract: A timing generation circuit (15) is formed integrally on the same glass substrate (11) together with a display area section (12) similarly to an H driver (13U) and a V driver (14), and timing pulses to be used by the H driver (13U) and the V driver (14) are produced based on timing data produced by a shift register (31U) of the H driver (13U) and a shift register (14A) of the V driver (14). The invention thereby provides a timing generation circuit which can contribute to miniaturization and reduction of the cost of the set and a display apparatus of the active matrix type in which the timing generation circuit is incorporated.Type: GrantFiled: December 6, 2001Date of Patent: May 17, 2005Assignee: Sony CorporationInventors: Yoshiharu Nakajima, Yasuhito Maki, Toshikazu Maekawa
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Comparator, display apparatus using comparator for driving system, and driving method for comparator
Patent number: 6590570Abstract: A comparator which can operate stably against an absolute value distribution of a threshold voltage among MOS transistors and has a wide allowable range against the threshold voltage dispersion and besides allows reduction in power consumption. The comparator employs a single MOS transistor, and a resistance element is connected between the drain electrode of the MOS transistor and a power supply. A capacitor is connected between the gate electrode of the MOS transistor and a dc potential point, and a switch is connected between the gate electrode and the drain electrode. A comparison reference level and comparison input data are inputted in a time series to the source electrode of the MOS transistor, and the MOS transistor performs a comparation operation.Type: GrantFiled: May 9, 2000Date of Patent: July 8, 2003Assignee: Sony CorporationInventor: Yasuhito Maki -
Publication number: 20030030736Abstract: When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping is generally supplied to an A/D converter as generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks âH1 and âH2 of a signal output by an empty transmission unit 13a by means of a clamp pulse âCLP1 and a sample/hold output Va for the second picture element or a subsequent one of an OPB unit 11a is clamped to a clamp level Vref by means of a clamp pulse âCLP2 so as to prevent a signal output Vout exceeding a reference voltage from being supplied to an A/D converter at a later stage.Type: ApplicationFiled: September 20, 2002Publication date: February 13, 2003Inventors: Satoshi Yoshihara, Yasuhito Maki
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Publication number: 20030001800Abstract: A timing generation circuit (15) is formed integrally on the same glass substrate (11) together with a display area section (12) similarly to an H driver (13U) and a V driver (14), and timing pulses to be used by the H driver (13U) and the V driver (14) are produced based on timing data produced by a shift register (31U) of the H driver (13U) and a shift register (14A) of the V driver (14). The invention thereby provides a timing generation circuit which can contribute to miniaturization and reduction of the cost of the set and a display apparatus of the active matrix type in which the timing generation circuit is incorporated.Type: ApplicationFiled: July 31, 2002Publication date: January 2, 2003Inventors: Yoshiharu Nakajima, Yasuhito Maki, Toshikazu Maekawa
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Patent number: 6480228Abstract: When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping is generally supplied to an A/D converter as generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal oputput by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.Type: GrantFiled: July 8, 1996Date of Patent: November 12, 2002Assignee: Sony CorporationInventors: Satoshi Yoshihara, Yasuhito Maki