Patents by Inventor Yasuhito Maki
Yasuhito Maki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5539536Abstract: A linear sensor for sampling vertically opposed pixels of a plurality of vertically arranged sensor rows substantially at a time. A plurality of horizontal transfer registers and a plurality of shift gates are provided to oppose the plurality of sensor rows. A vertical transfer register is provided at one end of the plurality of horizontal transfer registers. In the vertical transfer register, the signal charges which have been transferred by the plurality of horizontal transfer registers are transferred sequentially in vertical direction. A charge/voltage converter unit is provided at the output of the vertical transfer register. The signal charges accumulated in the vertically opposed pixels are sequentially transferred to the charge/voltage converter unit in a repetitive manner.Type: GrantFiled: March 18, 1993Date of Patent: July 23, 1996Assignee: Sony CorporationInventors: Yasuhito Maki, Motoaki Abe, Tadakuni Narabu, Hideo Nomura
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Patent number: 5536956Abstract: A charge transfer device formed on a semiconductor substrate comprising: a charge transfer section formed on the semiconductor substrate for transferring charges, a floating gate having a floating gate diffusion layer formed on the semiconductor substrate for accumulating the charges transferred from the charge transfer section, an output gate section formed between the charge transfer section and the floating gate on the semiconductor substrate, and a charge detecting circuit electrically connected to the floating gate for outputting a voltage corresponding to the amount of the charges accumulated in the floating gate diffusion layer, the output gate section having a first output gate region adjacent to the charge transfer means and a second output gate region adjacent to the floating gate diffusion layer, the first output gate region having a first output gate electrode formed thereon with an insulating film therebetween, the second output gate region having a second output gate electrode formed thereon witType: GrantFiled: June 7, 1995Date of Patent: July 16, 1996Assignee: Sony CorporationInventors: Seiichi Kawamoto, Yasuhito Maki, Tadakuni Narabu, Masahide Hirama
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Patent number: 5473155Abstract: The photometric sensor of the present invention includes a plurality of photoelectric conversion elements which accumulate electric charge according to the intensity of the light which is incident upon them; a CCD shift register, comprising a plurality of CCD (Charge Coupled Device) elements which correspond respectively to the plurality of photoelectric conversion elements, and at least one relay CCD element which does not correspond to any one of the photoelectric conversion elements, and which reads in the accumulated electric charges from the plurality of photoelectric conversion elements to the plurality of CCD elements and transmits them via the relay CCD element; a charge to voltage conversion circuit which converts the accumulated electric charges transmitted from the CCD shift register into photometric signals and outputs them in order; and a timing signal generation circuit which, when the photometric signals from the charge to voltage conversion circuit originating from the plurality of photoelectrType: GrantFiled: July 12, 1994Date of Patent: December 5, 1995Assignees: Nikon Corporation, Sony CorporationInventors: Hiroyuki Iwasaki, Tadao Takagi, Tetsuro Goto, Yasuhito Maki
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Patent number: 5455443Abstract: A CCD solid state imaging device has an overflow mechanism to discharge excess electric charges at the sensor section. An overflow level can be stabilized without adjustment. The CCD solid state imaging device includes an overflow barrier region for determining an amount of electric charges handled by a sensor section, and an overflow drain region for discharging excess electric charges at the sensor section adjacent to the sensor section. An intermediate region having the same potential as that of the sensor portion is provided between the overflow barrier region and the overflow drain region. Also, a CCD solid state imaging device includes linear sensors provided in a plurality of lines and vertical transfer registers provided at end of the linear sensors in the charge transfer direction of the horizontal transfer registers. When signal charges are overflowed in a part of the horizontal transfer register, signals of all pixels can be avoided from being destroyed.Type: GrantFiled: April 11, 1994Date of Patent: October 3, 1995Assignee: Sony CorporationInventors: Yasuhito Maki, Satoshi Yoshihara
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Patent number: 5227650Abstract: The present invention is to provide a CCD delay line in which a deterioration of a charge transfer efficiency can be reduced by maintaining a charge amount treated in a charge transfer section provided at the rear stage of an intermediate output section. According to an aspect of the present invention, in a charge transfer device having charge transfer sections of a plurality of stages consisting of electrode pairs of a transfer gate electrode and a storage gate electrode and at least one intermediate output section provided at the rear stage of a charge transfer section of a predetermined stage from the signal input side, a cross-sectional area of at least one of the transfer gate electrode and the storage gate electrode in the charge transfer section provided at the rear stage of the intermediate output section is selected to be larger than that in the charge transfer section provided at the front stage of the intermediate output section.Type: GrantFiled: January 23, 1992Date of Patent: July 13, 1993Assignee: Sony CorporationInventors: Katsunori Noguchi, Maki Sato, Tadakuni Narabu, Yasuhito Maki
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Patent number: 5210777Abstract: A charge coupled device is provided with a first signal input path for supplying an information signal for transfer through a delay line, which contain an inverting amplifier, and a second signal input path which has no inverting amplifier. The first and second signal input paths are arranged in parallel to each other. The charge coupled device also has a switching means associated with the first and second signal input paths so as to selectively establishing connection between one of the first and second signal input paths and the delay line so that non-inverted and inverted information signals can be selectively supplied to the delay line.Type: GrantFiled: April 16, 1990Date of Patent: May 11, 1993Assignee: Sony CorporationInventors: Tadakuni Narabu, Tetsuya Kondo, Yasuhito Maki, Katsunori Noguchi
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Patent number: 5189499Abstract: A charge-coupled device has a multi-layer structure insulating layer is formed beneath a transfer electrode, floating electrodes and an electrode adjacent the floating electrodes so that pin hole phenomenon in a charge transfer section of the charge coupled device can be successfully prevented. On the other hand, a sole-layer structure insulating layer is formed beneath a gate electrode of a peripheral component so that a threshold voltage of the gate electrode of the peripheral component can be successfully controlled at a desired value.Type: GrantFiled: October 8, 1991Date of Patent: February 23, 1993Assignee: Sony CorporationInventors: Akio Izumi, Yasuhito Maki, Tadakuni Narabu, Maki Sato, Takaji Otsu, Katsuyuki Saito
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Patent number: 5177772Abstract: An input structure of CCD comprises a primary register having an input gate and a source region and an automatic biasing system which generates a feedback signal to be fed back to input of the primary register. The output of the automatic biasing system is connected to one of the input gate and the source of the primary register for supplying the feedback signal thereto for adjusting input bias level of the primary register. The other one of the input gate and the source is connected to an information signal input terminal to receive therefrom an information signal to be transferred therethrough.Type: GrantFiled: December 4, 1991Date of Patent: January 5, 1993Assignee: Sony CorporationInventors: Tadakuni Narabu, Tetsuya Kondo, Yasuhito Maki, Katsunori Noguchi
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Patent number: 5124796Abstract: A charge coupled device has a circuit for handling a fundamental clock signal to produce a particular driving signal in the device, and independent power supply lines and/or ground lines. One power supply line and/or one ground line is exclusive for the circuit for handling the fundamental clock signal. The interference by the fundamental clock signal is prevented by the separation of power supply line and/or ground line.Type: GrantFiled: September 4, 1990Date of Patent: June 23, 1992Assignee: Sony CorporationInventor: Yasuhito Maki
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Patent number: 5086440Abstract: An input structure of CCD comprises a primary register having an input gate and a source region and an automatic biasing system which generates a feedback signal to be fed back to input of the primary register. The output of the automatic biasing system is connected to one of the input gate and the source of the primary register for supplying the feedback signal thereto for adjusting input bias level of the primary register. The other one of the input gate and the source is connected to an information signal input terminal to receive therefrom an information signal to be transferred therethrough.Type: GrantFiled: April 16, 1990Date of Patent: February 4, 1992Assignee: Sony CorporationInventors: Tadakuni Narabu, Tetsuya Kondo, Yasuhito Maki, Katsunori Noguchi
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Patent number: 5029189Abstract: A charge coupled device employs peak hold circuits for detecting electric charges transferred through reference registers for facilitating automatic iput bias control. The peak hold circuits are respectively connected to a pair of reference registers which are so designed that one of the reference registers has a given maximum rating and the other reference register is adapted to transfer electric charge having a given fraction of the maximum charge rating of the aforementioned one of registers. The peak hold circuits provide peak values of the outputs of the reference registers to a comparator which feedback controls the input bias of the one of the register. This controlled bias is also applied to an input bias for a signal register which is designed for transferring input electric charge.Type: GrantFiled: September 29, 1987Date of Patent: July 2, 1991Assignee: Sony CorporationInventors: Maki Sato, Tadakuni Narabu, Yasuhito Maki
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Patent number: 4990862Abstract: An output stage of a solid-state image pick-up device, such as a CCD solid-state image pick-up device is accurately operable even under a lower source source voltage is easy to design and does not require substantial precision in production. The improved output stage construction of a solid-state image pick-up device, according to the present invention, has a buffer circuit, connected to at least one of a input side or a output side of an output stage circuit component, such as an amplifier circuit, and a low-pass filter source source. The buffer circuit is so designed as to have a constant DC level and a gain about 1.Type: GrantFiled: January 19, 1988Date of Patent: February 5, 1991Assignee: Sony CorporationInventors: Tadakuni Narabu, Yasuhito Maki, Tetsuya Kondo
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Patent number: 4939560Abstract: A charge transfer device, suitable for use, for example, in a solid state imager device, having a floating gate electrode in a charge detecting section, a protruding portion provided in at least one of the floating gate electrodes or a gate electrode arranged adjacent to the floating gate electrode, wherein the floating gate electrode and the gate electrode arranged adjacent to the floating gate electrode overlap each other at the protruding portion within an insulating layer, and whereby the parasitic capacitance associated with the floating gate electrode is decreased and the charge voltage converting gain is increased, rendering it possible to obtain an image signal with a good signal/noise ratio, when the charge transfer device is used for a solid state imager device.Type: GrantFiled: March 29, 1989Date of Patent: July 3, 1990Assignee: Sony CorporationInventors: Tadakuni Narabu, Yasuhito Maki, Tetsuya Kondo