Abstract: A surface emitting quantum cascade laser includes an active layer and a first semiconductor layer. The active layer includes a plurality of quantum well layers and is capable of emitting laser light by intersubband transition. The first surface includes an internal region and an outer peripheral region. Grating pitch of the first pits is m times grating pitch of the second pits. The outer peripheral region surrounds the internal region. A first planar shape of an opening end of the first pit is asymmetric with respect to a line passing through barycenter of the first planar shape and is parallel to at least one side of the first two-dimensional grating. A second planar shape of an opening end of the second pit is symmetric with respect to each of lines passing through barycenter of the second planar shape and is parallel to either side of the second two-dimensional grating.

Abstract: A surface emitting quantum cascade laser includes an active layer and a first semiconductor layer. The active layer includes a plurality of quantum well layers and is capable of emitting laser light by intersubband transition. The first surface includes an internal region and an outer peripheral region. Grating pitch of the first pits is m times grating pitch of the second pits. The outer peripheral region surrounds the internal region. A first planar shape of an opening end of the first pit is asymmetric with respect to a line passing through barycenter of the first planar shape and is parallel to at least one side of the first two-dimensional grating. A second planar shape of an opening end of the second pit is symmetric with respect to each of lines passing through barycenter of the second planar shape and is parallel to either side of the second two-dimensional grating.

Abstract: A substrate including a photonic crystal has a compound semiconductor, dielectric layers, and a first semiconductor layer. The dielectric layers are provided on a surface of the compound semiconductor substrate and disposed at each grating point of a two-dimensional diffraction grating, each of the dielectric layers having an asymmetric shape in relation to at least one edge of the two-dimensional diffraction grating and having a refractive index lower than a refractive index of the compound semiconductor substrate. The first semiconductor layer includes a flat first face covering the dielectric layers and the surface of the compound semiconductor substrate, a layer constituting the first face containing a material capable of being lattice matched to a material constituting the compound semiconductor substrate.

Abstract: A surface emitting quantum cascade laser includes an active layer and a first semiconductor layer. The active layer includes a plurality of quantum well layers and is capable of emitting laser light by intersubband transition. The first surface includes an internal region and an outer peripheral region. Grating pitch of the first pits is m times grating pitch of the second pits. The outer peripheral region surrounds the internal region. A first planar shape of an opening end of the first pit is asymmetric with respect to a line passing through barycenter of the first planar shape and is parallel to at least one side of the first two-dimensional grating. A second planar shape of an opening end of the second pit is symmetric with respect to each of lines passing through barycenter of the second planar shape and is parallel to either side of the second two-dimensional grating.

Abstract: A substrate including a photonic crystal has a compound semiconductor, dielectric layers, and a first semiconductor layer. The dielectric layers are provided on a surface of the compound semiconductor substrate and disposed at each grating point of a two-dimensional diffraction grating, each of the dielectric layers having an asymmetric shape in relation to at least one edge of the two-dimensional diffraction grating and having a refractive index lower than a refractive index of the compound semiconductor substrate. The first semiconductor layer includes a flat first face covering the dielectric layers and the surface of the compound semiconductor substrate, a layer constituting the first face containing a material capable of being lattice matched to a material constituting the compound semiconductor substrate.

Abstract: A surface emitting quantum cascade laser includes an active layer and a first semiconductor layer. The active layer includes a plurality of quantum well layers and is capable of emitting laser light by intersubband transition. The first surface includes an internal region and an outer peripheral region. Grating pitch of the first pits is m times grating pitch of the second pits. The outer peripheral region surrounds the internal region. A first planar shape of an opening end of the first pit is asymmetric with respect to a line passing through barycenter of the first planar shape and is parallel to at least one side of the first two-dimensional grating. A second planar shape of an opening end of the second pit is symmetric with respect to each of lines passing through barycenter of the second planar shape and is parallel to either side of the second two-dimensional grating.

Abstract: According to one embodiment, a method for producing a mask layout of an exposure mask for forming wiring of an integrated circuit device, includes estimating shape of the wiring formed based on an edge of a pattern included in an initial layout of the exposure mask. The method includes modifying shape of the edge if the estimated shape of the wiring does not satisfy a requirement.

Abstract: According to one embodiment, a semiconductor device includes: a substrate including silicon; and a first element provided on the substrate and extending in a thickness direction of the substrate, a center position of an end face on the substrate side of the first element and a center position of an end face on an opposite side of the substrate side of the first element being different in a direction parallel to a major surface of the substrate.

Abstract: According to one embodiment, a production method for a mask layout of an exposure mask includes evaluating a candidate layout by comparison between an imaged image group and a reference image group. The imaged image group is composed of a plurality of imaged images of patterns formed by performing lithography under a plurality of levels of exposure condition using the candidate layout. The reference image group is composed of a plurality of reference images produced by simulation on assumption of a plurality of levels of the exposure condition.

Abstract: According to one embodiment, an exposure tolerance estimation method is disclosed. The method can include setting a plurality of regions along a first surface of a substrate. The method can form a plurality of patterns for estimation by performing exposure on each of the regions using at least three levels of exposure condition using an exposure mask. The method can measure dimensions of the patterns for estimation and find relationships between the exposure condition and the dimensions. The method can select a first region from the regions. In the first region, a first dimension of a first pattern for estimation formed by exposure using a first exposure condition of an intermediate level out of the at least three levels falls within a previously set range. In addition, the method can calculate an exposure tolerance from a relationship between the first exposure condition and the first dimension.

Abstract: According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality of first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires.

Abstract: According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality at first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires.

Abstract: According to one embodiment, an exposure tolerance estimation method is disclosed. The method can include setting a plurality of regions along a first surface of a substrate. The method can form a plurality of patterns for estimation by performing exposure on each of the regions using at least three levels of exposure condition using an exposure mask. The method can measure dimensions of the patterns for estimation and find relationships between the exposure condition and the dimensions. The method can select a first region from the regions. In the first region, a first dimension of a first pattern for estimation formed by exposure using a first exposure condition of an intermediate level out of the at least three levels falls within a previously set range. In addition, the method can calculate an exposure tolerance from a relationship between the first exposure condition and the first dimension.

Abstract: According to one embodiment, a method for producing a mask layout of an exposure mask for forming wiring of an integrated circuit device, includes estimating shape of the wiring formed based on an edge of a pattern included in an initial layout of the exposure mask. The method includes modifying shape of the edge if the estimated shape of the wiring does not satisfy a requirement.

Abstract: According to one embodiment, a production method for a mask layout of an exposure mask includes evaluating a candidate layout by comparison between an imaged image group and a reference image group. The imaged image group is composed of a plurality of imaged images of patterns formed by performing lithography under a plurality of levels of exposure condition using the candidate layout. The reference image group is composed of a plurality of reference images produced by simulation on assumption of a plurality of levels of the exposure condition.

Abstract: A semiconductor device manufacturing method includes applying illumination light to a photomask, and projecting diffracted light components from the photomask via a projection optical system to form a photoresist pattern on a substrate. The photomask includes a plurality of opening patterns which are arranged on each of a plurality of parallel lines at regular second intervals in a second direction and which have regular first intervals in a first direction perpendicular to the second direction. The plurality of opening patterns arranged on the adjacent ones of the plurality of parallel lines are displaced from each other half the second interval in the second direction. Moreover, the dimensions of the plurality of opening patterns and the complex amplitude transmittance of nontransparent region in the photomask are set so that three of the diffracted light components passing through the pupil of the projection optical system have equal amplitude.

Abstract: According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality at first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires.

Abstract: In one embodiment, a photomask designing method for creating a pattern layout having an assist pattern placed around a design pattern is disclosed. The method can place a plurality of evaluation points around the design pattern and set an evaluation index for imaging properties of the design pattern on an imaging surface. The method can combine a light intensity distribution of the design pattern with light intensity distributions of the evaluation points to obtain a light intensity distribution on the imaging surface and evaluate the light intensity distribution on the imaging surface using the evaluation index to determine a region having an effective evaluation point placed. In addition, the method can determine a placement condition for the assist pattern based on the region where the effective evaluation point is placed and place the assist pattern around the design pattern based on the placement condition to create the pattern layout.

Abstract: A semiconductor device manufacturing method includes applying illumination light to a photomask, and projecting diffracted light components from the photomask via a projection optical system to form a photoresist pattern on a substrate. The photomask includes a plurality of opening patterns which are arranged on each of a plurality of parallel lines at regular second intervals in a second direction and which have regular first intervals in a first direction perpendicular to the second direction. The plurality of opening patterns arranged on the adjacent ones of the plurality of parallel lines are displaced from each other half the second interval in the second direction. Moreover, the dimensions of the plurality of opening patterns and the complex amplitude transmittance of nontransparent region in the photomask are set so that three of the diffracted light components passing through the pupil of the projection optical system have equal amplitude.

Abstract: According to one embodiment, a method is disclosed for determining position of an auxiliary pattern on a photomask. The method can include generating a first set for each of three or more imaging positions of an exposure optical system. The method can include generating a second set for each of the three or more imaging positions by inverse Fourier transforming each of the first set. The method can include calculating a second order differential with respect to the imaging position of an index indicating amplitude of light belonging to the second set. In addition, the method can include extracting a position where the second order differential assumes an extremal value on an imaging plane of the exposure optical system. At least part of positions on the photomask each corresponding to the position assuming the extremal value on the imaging plane is used as a formation position of the auxiliary pattern.