Patents by Inventor Yasunobu Kai
Yasunobu Kai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8293456Abstract: A semiconductor device manufacturing method includes applying illumination light to a photomask, and projecting diffracted light components from the photomask via a projection optical system to form a photoresist pattern on a substrate. The photomask includes a plurality of opening patterns which are arranged on each of a plurality of parallel lines at regular second intervals in a second direction and which have regular first intervals in a first direction perpendicular to the second direction. The plurality of opening patterns arranged on the adjacent ones of the plurality of parallel lines are displaced from each other half the second interval in the second direction. Moreover, the dimensions of the plurality of opening patterns and the complex amplitude transmittance of nontransparent region in the photomask are set so that three of the diffracted light components passing through the pupil of the projection optical system have equal amplitude.Type: GrantFiled: February 20, 2009Date of Patent: October 23, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Fukuhara, Takaki Hashimoto, Kazuyuki Masukawa, Yasunobu Kai
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Patent number: 8288812Abstract: According to one embodiment, a semiconductor device includes a substrate, conductive members, an interlayer insulating film, and a plurality of contacts. The conductive members are provided in an upper portion of the substrate or above the substrate to extend in one direction. The interlayer insulating film is provided on the substrate and the conductive members. The plurality of contacts is provided in the interlayer insulating film. In a first region on the substrate, the contacts are located at some of lattice points of an imaginary first lattice. In a second region on the substrate, the contacts are located at some of lattice points of an imaginary second lattice. The second lattice is different from the first lattice. Each of the first lattice and the second lattice includes some of the lattice points located on the conductive members or on an extension region extended in the one direction of the conductive members.Type: GrantFiled: August 30, 2010Date of Patent: October 16, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yasunobu Kai, Takaki Hashimoto
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Publication number: 20120070985Abstract: According to one embodiment, an exposure method is disclosed. The method can include applying light to a photomask by an illumination. The method can include converging diffracted beams emitted from the photomask by a lens. In addition, the method can include imaging a plurality of point images on an exposure surface. On the photomask, a light transmitting region is formed at a lattice point represented by nonorthogonal unit cell vectors, and in the illumination, a light emitting region is set so that three or more of the diffracted beams pass through positions equidistant from center of a pupil of the lens.Type: ApplicationFiled: September 15, 2011Publication date: March 22, 2012Inventors: Takaki Hashimoto, Kazuya Fukuhara, Toshiya Kotani, Yasunobu Kai
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Publication number: 20120064732Abstract: According to one embodiment, a method is disclosed for determining position of an auxiliary pattern on a photomask. The method can include generating a first set for each of three or more imaging positions of an exposure optical system. The method can include generating a second set for each of the three or more imaging positions by inverse Fourier transforming each of the first set. The method can include calculating a second order differential with respect to the imaging position of an index indicating amplitude of light belonging to the second set. In addition, the method can include extracting a position where the second order differential assumes an extremal value on an imaging plane of the exposure optical system. At least part of positions on the photomask each corresponding to the position assuming the extremal value on the imaging plane is used as a formation position of the auxiliary pattern.Type: ApplicationFiled: September 12, 2011Publication date: March 15, 2012Inventors: Yasunobu Kai, Katsuyoshi Kodera
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Patent number: 7941782Abstract: In a pattern layout which includes a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed parallel to one anther and uniformly arranged with constant width at a constant pitch and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly arranged, and a second device pattern arranged adjacent to the end portion of the non-uniformly repeated pattern group in an arrangement direction thereof and having second lines and second spaces whose widths are larger than the widths of the first lines and first spaces of the non-uniformly repeated pattern group, at least part of the widths of the first lines and the first spaces of the non-uniformly repeated pattern group is made larger than the width of the first line or the width of the first space of the uniformly repeated pattern group.Type: GrantFiled: November 21, 2007Date of Patent: May 10, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yasunobu Kai, Kazuo Hatakeyama, Hidefumi Mukai, Hiromitsu Mashita, Koji Hashimoto
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Patent number: 7934175Abstract: A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate; defining an adjustable parameter of another to-be-adjusted manufacturing; obtaining a second shape of the pattern formed on the substrate; calculating a difference amount between a reference finished shape and a to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; and outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter.Type: GrantFiled: April 4, 2008Date of Patent: April 26, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Toshiya Kotani, Yasunobu Kai, Soichi Inoue, Satoshi Tanaka, Shigeki Nojima, Kazuyuki Masukawa, Koji Hashimoto
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Publication number: 20110072402Abstract: In one embodiment, a photomask designing method for creating a pattern layout having an assist pattern placed around a design pattern is disclosed. The method can place a plurality of evaluation points around the design pattern and set an evaluation index for imaging properties of the design pattern on an imaging surface. The method can combine a light intensity distribution of the design pattern with light intensity distributions of the evaluation points to obtain a light intensity distribution on the imaging surface and evaluate the light intensity distribution on the imaging surface using the evaluation index to determine a region having an effective evaluation point placed. In addition, the method can determine a placement condition for the assist pattern based on the region where the effective evaluation point is placed and place the assist pattern around the design pattern based on the placement condition to create the pattern layout.Type: ApplicationFiled: August 4, 2010Publication date: March 24, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yasunobu KAI
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Publication number: 20110049601Abstract: According to one embodiment, a semiconductor device includes a substrate, conductive members, an interlayer insulating film, and a plurality of contacts. The conductive members are provided in an upper portion of the substrate or above the substrate to extend in one direction. The interlayer insulating film is provided on the substrate and the conductive members. The plurality of contacts is provided in the interlayer insulating film. In a first region on the substrate, the contacts are located at some of lattice points of an imaginary first lattice. In a second region on the substrate, the contacts are located at some of lattice points of an imaginary second lattice. The second lattice is different from the first lattice. Each of the first lattice and the second lattice includes some of the lattice points located on the conductive members or on an extension region extended in the one direction of the conductive members.Type: ApplicationFiled: August 30, 2010Publication date: March 3, 2011Inventors: Yasunobu Kai, Takaki Hashimoto
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Publication number: 20100304568Abstract: A pattern forming method includes forming a first photoresist on an underlying region, forming a second photoresist on the first photoresist, the second photoresist having an exposure sensitivity which is different from an exposure sensitivity of the first photoresist, radiating exposure light on the first and second photoresists via a photomask including a first transmissive region and a second transmissive region which cause a phase difference of 180° between transmissive light components passing therethrough, the first transmissive region and the second transmissive region being provided in a manner to neighbor in an irradiation region, and developing the first and second photoresists which have been irradiated with the exposure light, thereby forming a structure includes a first region where the underlying region is exposed, a second region where the first photoresist is exposed and a third region where the first photoresist and the second photoresist are left.Type: ApplicationFiled: April 1, 2010Publication date: December 2, 2010Inventors: Seiro MIYOSHI, Yasunobu Kai, Kentaro Matsunaga, Keisuke Kikutani, Eishi Shiobara, Shinya Takahashi
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Publication number: 20100202181Abstract: A semiconductor memory device includes a semiconductor substrate on which memory cells are formed. Interconnects are arranged along a first direction above the semiconductor substrate, and have regular intervals along a second direction perpendicular to the first direction. Interconnect contacts connect the interconnects and the semiconductor substrate, are arranged on three or more rows. The center of each of two of the interconnect contacts which are connected to the interconnects adjacent in the second direction deviate from each other along the first direction.Type: ApplicationFiled: September 17, 2009Publication date: August 12, 2010Inventors: Takaki HASHIMOTO, Hidefumi Mukai, Yasunobu Kai, Toshiya Kotani
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Patent number: 7682757Abstract: A pattern layout for forming an integrated circuit includes a first device pattern, a second device pattern, and an auxiliary pattern. The first device pattern includes a line and a space alternately arrayed on a fixed pitch having regular intervals in a first direction. The second device pattern is disposed on the fixed pitch and separated from the first device pattern in the first direction. The second device pattern has a pattern width an odd-number times larger than the regular intervals of the fixed pitch, wherein the odd-number is set to be three or more. The auxiliary pattern is disposed on the fixed pitch and within the second device pattern and configured not to be resolved by light exposure.Type: GrantFiled: April 12, 2006Date of Patent: March 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiromitsu Mashita, Tadahito Fujisawa, Minoru Inomoto, Koji Hashimoto, Yasunobu Kai
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Publication number: 20090220894Abstract: A semiconductor device manufacturing method includes applying illumination light to a photomask, and projecting diffracted light components from the photomask via a projection optical system to form a photoresist pattern on a substrate. The photomask includes a plurality of opening patterns which are arranged on each of a plurality of parallel lines at regular second intervals in a second direction and which have regular first intervals in a first direction perpendicular to the second direction. The plurality of opening patterns arranged on the adjacent ones of the plurality of parallel lines are displaced from each other half the second interval in the second direction. Moreover, the dimensions of the plurality of opening patterns and the complex amplitude transmittance of nontransparent region in the photomask are set so that three of the diffracted light components passing through the pupil of the projection optical system have equal amplitude.Type: ApplicationFiled: February 20, 2009Publication date: September 3, 2009Inventors: Kazuya FUKUHARA, Takaki HASHIMOTO, Kazuyuki MASUKAWA, Yasunobu KAI
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Publication number: 20090142706Abstract: A method of manufacturing a semiconductor includes performing exposure using a first photomask having a pattern line in which hole patterns and assist patterns not transferred onto the semiconductor substrate are arrayed at an equal pitch on the mask, the pitch being converted a first pitch Phole on the substrate when the mask patterns are transferred on the substrate, and performing exposure using a second photomask having a pattern line in which wiring patterns are arrayed at an equal pitch on the mask, the pitch being converted a second pitch Pline on the substrate when the mask patterns are transferred on the substrate, wherein m×Pline=n×Phole and m,n(m>n) are integers.Type: ApplicationFiled: October 24, 2008Publication date: June 4, 2009Inventors: Kazuyuki Masukawa, Koji Hashimoto, Kenji Kawano, Yasunobu Kai
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Publication number: 20080250381Abstract: A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device so as to fall within a range of a predetermined permissible variation and defining the adjusted parameter as a reference parameter of the reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate using the reference manufacturing device from a mask to form the pattern on the substrate when the reference parameter is set to the reference manufacturing device and defining the obtained first shape as a reference finished shape; defining an adjustable parameter of another to-be-adjusted manufacturing device as a to-be-adjusted parameter of the to-be-adjusted manufacturing device; obtaining a second shape of the pattern formed on the substrate using the to-be-adjusted manufacturiType: ApplicationFiled: April 4, 2008Publication date: October 9, 2008Inventors: Toshiya KOTANI, Yasunobu Kai, Soichi Inoue, Satoshi Tanaka, Shigeki Nojima, Kazuyuki Masukawa, Koji Hashimoto
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Publication number: 20080137421Abstract: In a pattern layout which includes a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed parallel to one anther and uniformly arranged with constant width at a constant pitch and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly arranged, and a second device pattern arranged adjacent to the end portion of the non-uniformly repeated pattern group in an arrangement direction thereof and having second lines and second spaces whose widths are larger than the widths of the first lines and first spaces of the non-uniformly repeated pattern group, at least part of the widths of the first lines and the first spaces of the non-uniformly repeated pattern group is made larger than the width of the first line or the width of the first space of the uniformly repeated pattern group.Type: ApplicationFiled: November 21, 2007Publication date: June 12, 2008Inventors: Yasunobu KAI, Kazuo Hatakeyama, Hidefumi Mukai, Hiromitsu Mashita, Koji Hashimoto
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Publication number: 20060228636Abstract: A pattern layout for forming an integrated circuit includes a first device pattern, a second device pattern, and an auxiliary pattern. The first device pattern includes a line and a space alternately arrayed on a fixed pitch having regular intervals in a first direction. The second device pattern is disposed on the fixed pitch and separated from the first device pattern in the first direction. The second device pattern has a pattern width an odd-number times larger than the regular intervals of the fixed pitch, wherein the odd-number is set to be three or more. The auxiliary pattern is disposed on the fixed pitch and within the second device pattern and configured not to be resolved by light exposure.Type: ApplicationFiled: April 12, 2006Publication date: October 12, 2006Inventors: Hiromitsu Mashita, Tadahito Fujisawa, Minoru Inomoto, Koji Hashimoto, Yasunobu Kai
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Patent number: 5128465Abstract: A cephem derivative represented by the following formula: ##STR1## wherein R.sub.1 means a fluorine-substituted lower alkyl and A.sub.1 denotes a cyclic or acyclic ammonio group, or a non-toxic salt thereof, is prepared by reacting a compound represented by the following formula: ##STR2## wherein A.sub.1 has the same meaning as defined above, with another compound represented by the following formula: ##STR3## wherein R.sub.1 has the same meaning as defined above, and if necessary, removing the protecting groups.Type: GrantFiled: January 22, 1990Date of Patent: July 7, 1992Assignee: Eisai Co., Ltd.Inventors: Takashi Kamiya, Toshihiko Naito, Yuuki Komatu, Yasunobu Kai, Takaharu Nakamura, Manabu Sasho, Shigeto Negi, Isao Sugiyama, Kanemasa Katsu, Hiroshi Yamauchi
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Patent number: 5089491Abstract: A 3-propenylcephem derivative of the following formula: ##STR1## wherein R.sub.1 represents a fluoro-substituted lower alkyl group or a cyano-substituted lower alkyl group, and A represents a cyclic or an acylic ammonio group, or a pharmaceutically acceptable salt thereof, exhibiting excellent anti-bacterial activities against both Gram-positive bacteria and Gram-negative bacteria; Process for the preparation thereof; Anti-bacterial composition; Intermediate for the 3-propenylcephem derivative; and Process for the preparation of the intermediate.Type: GrantFiled: January 11, 1990Date of Patent: February 18, 1992Assignee: Eisai Co., Ltd.Inventors: Takashi Kamiya, Toshihiko Naito, Shigeto Negi, Yuuki Komatu, Yasunobu Kai, Takaharu Nakamura, Isao Sugiyama, Yoshimasa Machida, Seiichiro Nomoto, Kyosuke Kitoh, Kanemasa Katsu, Hiroshi Yamauchi
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Patent number: 5006649Abstract: A 3-propenylcephem derivative of the following formula: ##STR1## wherein R.sub.1 represents a fluoro-substituted lower alkyl group or a cyano-substituted lower alkyl group, and A represents a cyclic or an acylic ammonio group, or a pharmaceutically acceptable salt thereof, exhibiting excellent anti-bacterial activities against both Gram-positive bacteria and Gram-negative bacteria; Process for the preparation thereof; Anti-bacterial composition; Intermediate for the 3-propenylcephem derivative; and Process for the preparation of the intermediate.Type: GrantFiled: January 11, 1990Date of Patent: April 9, 1991Assignee: Eisai, Co.Inventors: Takashi Kamiya, Toshihiko Naito, Shigeto Negi, Yuuki Komatu, Yasunobu Kai, Takaharu Nakamura, Isao Sugiyama, Yoshimasa Machida, Seiichiro Nomoto, Kyosuke Kitoh, Kanemasa Katsu, Hiroshi Yamauchi
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Patent number: 4929612Abstract: Novel thiadiazolylacetamide cephem derivatives of the following formula are described. ##STR1## wherein A represents a quaternary ammonio group; or a pharmaceutically acceptable salt thereof. These novel compounds are useful as antibacterial agents, because they have a broad antibacterial spectrum ranging from gram-negative bacteria to gram-positive bacteria. Processes for the preparation of these novel compounds are also described.Type: GrantFiled: April 14, 1988Date of Patent: May 29, 1990Assignee: Eisai Co., Ltd.Inventors: Yoshimasa Machida, Shigeto Negi, Takashi Kamiya, Yuuki Komatu, Isao Sugiyama, Yasunobu Kai, Takaharu Nakamura, Toshihiko Naito, Kyosuke Kitoh, Kanemasa Katsu, Hiroshi Yamauchi