Abstract: In a DC/DC converter, a control circuit determines an upper limit value of an inductor current based on a load current and an input dc voltage, and changes at least one of an on time and an off time of a switching element in such a manner that the detected inductor current does not exceed the upper limit value.

Abstract: In a DC/DC converter, a control circuit determines an upper limit value of an inductor current based on a load current and an input dc voltage, and changes at least one of an on time and an off time of a switching element in such a manner that the detected inductor current does not exceed the upper limit value.

Abstract: A semiconductor integrated circuit device is provided, in which a node from which an output signal of a level shifter is sent can be initialized such that the potential thereof be set at a desired logic level at the time of power supply. The semiconductor integrated circuit device includes a level shifter 6 and two capacitors N10 and C0. The level shifter 6 receives an input signal and converts the received signal to a signal having a voltage amplitude greater than that of the received signal, then to provide the signal to a node D3. The capacitor N10 is connected to the node D3, and the capacitor C0 is connected in series with the capacitor N10. The capacitor N10 is formed of a MOS transistor having a gate connected to the node D3 and a source and a drain both connected to the capacitor C0.

Abstract: A local sense amplifier drives a global bit line pair by potentials of data storage nodes when a global word line attains an H level. A global sense amplifier amplifies the potential difference of data storage nodes when a global sense enable signal attains an H level. The global sense enable signal is inverted by an inverter to be provided to a global word driver. When the global word line attains an L level by the global word driver, the local sense amplifier suppresses the drive of the global bit line pair.

Abstract: Core circuitry is configured with a transistor formed of a gate oxide film of a thin film thickness, receiving a first power supply voltage to operate. Interface circuitry is configured with a transistor formed of a gate oxide film of a thick film thickness, receiving a second power supply voltage to operate. An appropriate voltage is supplied to the substrate of a P channel MOS transistor and an N channel MOS transistor which are output drivers, based on a mode select signal set according to the voltage level of the second power supply voltage, whereby a PNP parasitic bipolar transistor and an NPN parasitic bipolar transistor are driven at high speed. Although the interface circuitry of a semiconductor device is configured with a transistor formed of a thick gate oxide film, the speed will not be degraded even if the power supply voltage is set at a low voltage level.

Abstract: In a bus circuit which includes a plurality of signal lines, insertion pattern &agr;, which provides repeaters in only an odd numbered series of signal lines, and insertion pattern &bgr;, of which the segment length is equal to that of pattern &agr; and which provides repeaters to only an even numbered series of signal lines, are arranged in an alternating manner in accordance with the length of the signal lines. As a result, the segments during which data signals on the neighboring signal lines run together in opposite phases become half the entire length of the signal lines. Therefore, this bus circuit can prevent the operational speed from becoming slowed.

Abstract: A local sense amplifier drives a global bit line pair by potentials of data storage nodes when a global word line attains an H level. A global sense amplifier amplifies the potential difference of data storage nodes when a global sense enable signal attains an H level. The global sense enable signal is inverted by an inverter to be provided to a global word driver. When the global word line attains an L level by the global word driver, the local sense amplifier suppresses the drive of the global bit line pair.

Abstract: Dummy cells are divided into a plurality of divided dummy columns, and divided dummy bit lines are arranged corresponding to the divided dummy columns. These divided dummy bit lines are provided with dummy sense amplifiers that drive a sense control line transmitting a sense enable signal activating a sense amplifier. A faster activation timing of the sense amplifier can be achieved.

Abstract: Provided is a comparator for quickly comparing a tag information stored in a cache memory with a reference tag information outputted from a CPU. A sense enable signal (SE), which controls the active state of a sense amplifier (SA) performing the output of a tag information (TM) stored in a TAG-RAM, is used to compare the tag information (TM) with a reference tag information (TC) outputted from the CPU.

Abstract: Even if a power supply potential VDD of a core section is set in an off state, a latch of a level conversion circuit holds a value corresponding to an output. It is, therefore, possible for a semiconductor device to hold an output state of an output node. Thereafter, an enable signal is deactivated, whereby the output node can be set in a high impedance state and a bus or the like can be released to the other device.

Abstract: The dummy cell of the SRAM corresponds to a normal memory cell of which first and second P-channel MOS transistors for loading are replaced by the first and the second N-channel MOS transistors, of which gate and source are provided with power supply potential and ground potential, respectively. When a word line rises to “H” level, third and fourth N-channel MOS transistors for accessing are rendered conductive, to pass current from dummy bit line to a line of ground potential via the third N-channel MOS transistor, the first N-channel MOS transistor, and a fifth N-channel MOS transistor for driving. Accordingly, speed of potential decrease of the dummy bit line may be faster than that of bit line. Hence, operational timing can easily be optimized, and operational margin can be increased.

Abstract: The dummy cell of the SRAM corresponds to a normal memory cell of which first and second P-channel MOS transistors for loading are replaced by the first and the second N-channel MOS transistors, of which gate and source are provided with power supply potential and ground potential, respectively. When a word line rises to “H” level, third and fourth N-channel MOS transistors for accessing are rendered conductive, to pass current from dummy bit line to a line of ground potential via the third N-channel MOS transistor, the first N-channel MOS transistor, and a fifth N-channel MOS transistor for driving. Accordingly, speed of potential decrease of the dummy bit line may be faster than that of bit line. Hence, operational timing can easily be optimized, and operational margin can be increased.

Abstract: Dummy cells each having the same layout as a normal memory cell are aligned in a row direction to the normal memory cells, and are arranged in rows and columns. In each dummy cell column, a dummy bit line is arranged, and a plurality of dummy cells are simultaneously selected and connected to the corresponding dummy bit line when one word line is selected. A voltage detecting circuit detects the potentials on the dummy bit lines to determine timing of activation of a sense amplifier. In the semiconductor memory device, the potential on the dummy bit line can be changed at high speed, and internal data read timing can be optimized independent of a structure of a memory cell array.

Abstract: Dummy cells are divided into a plurality of divided dummy columns, and divided dummy bit lines are arranged corresponding to the divided dummy columns. These divided dummy bit lines are provided with dummy sense amplifiers that drive a sense control line transmitting a sense enable signal activating a sense amplifier. A faster activation timing of the sense amplifier can be achieved.

Abstract: Core circuitry is configured with a transistor formed of a gate oxide film of a thin film thickness, receiving a first power supply voltage to operate. Interface circuitry is configured with a transistor formed of a gate oxide film of a thick film thickness, receiving a second power supply voltage to operate. An appropriate voltage is supplied to the substrate of a P channel MOS transistor and an N channel MOS transistor which are output drivers, based on a mode select signal set according to the voltage level of the second power supply voltage, whereby a PNP parasitic bipolar transistor and an NPN parasitic bipolar transistor are driven at high speed. Although the interface circuitry of a semiconductor device is configured with a transistor formed of a thick gate oxide film, the speed will not be degraded even if the power supply voltage is set at a low voltage level.

Abstract: Dummy cells each having the same layout as a normal memory cell are aligned in a row direction to the normal memory cells, and are arranged in rows and columns. In each dummy cell column, a dummy bit line is arranged, and a plurality of dummy cells are simultaneously selected and connected to the corresponding dummy bit line when one word line is selected. A voltage detecting circuit detects the potentials on the dummy bit lines to determine timing of activation of a sense amplifier. In the semiconductor memory device, the potential on the dummy bit line can be changed at high speed, and internal data read timing can be optimized independent of a structure of a memory cell array.

Abstract: A semiconductor integrated circuit device is provided, in which a node from which an output signal of a level shifter is sent can be initialized such that the potential thereof be set at a desired logic level at the time of power supply.

Abstract: Even if a power supply potential VDD of a core section is set in an off state, a latch of a level conversion circuit holds a value corresponding to an output. It is, therefore, possible for a semiconductor device to hold an output state of an output node. Thereafter, an enable signal is deactivated, whereby the output node can be set in a high impedance state and a bus or the like can be released to the other device.

Abstract: In a bus circuit which includes a plurality of signal lines, insertion pattern &agr;, which provides repeaters in only an odd numbered series of signal lines, and insertion pattern &bgr;, of which the segment length is equal to that of pattern &agr; and which provides repeaters to only an even numbered series of signal lines, are arranged in an alternating manner in accordance with the length of the signal lines. As a result, the segments during which data signals on the neighboring signal lines run together in opposite phases become half the entire length of the signal lines. Therefore, this bus circuit can prevent the operational speed from becoming slowed.

Abstract: A circuit module includes a connector terminal (4A) provided on a front surface of a printed wiring board (2) and connected to a data pin (DQt) of a memory IC (3) through an interconnect line (5a). A conductive connector terminal (4c) corresponds to the connector terminal (4a) and is provided on a back surface of the printed wiring board (2). A through hole (16) extends between part of the front surface of the printed wiring board (2) where the connector terminal (4a) is formed and part of the back surface thereof where the conductive connector terminal (4c) is formed. A conductor fills the through hole (16), thereby suppressing skews resulting from a difference in interconnect line length on the circuit module and decreasing a stub capacitance to achieve the reduction in power consumption.