Abstract: When a pair of word lines 1 and 2 change from a selected state to a non selected state, a word line discharging circuit 10 enables a transistor 15 to conduct during a period when this pair of word lines 1 and 2 are maintained at the highest potential compared with the other pairs of word lines, so that the pair of word lines 1 and 2 are discharged by means of a first discharging current source 11. The word line discharging circuit 10 enables a transistor 16 to conduct after another pair of word lines attain the highest potential, so that the pair of word lines 1 and 2 are discharged by means of a second discharging current source 12.

Abstract: A semiconductor memory device having a plurality of word line pairs and drain lines, a plurality of bit line pairs, and a plurality of memory cells connected to both of the word line pairs and the bit line pairs at the cross points thereof, comprising: a first and a second word line provided as the word line pair, a memory cell including a first and a second multi-emitter transistor whose commonly connected emitters are connected to the drain line, first and second resistors where one of their ends are connected between the collectors of the first and second multi-emitter transistors respectively, and where their other ends are both connected to the first word line and the bases of the second and first multi-emitter transistors are connected to the other's collectors, respectively, and first and second diodes such as Schottky barrier diodes are connected between the collectors of the first and second multi-emitter transistors and the second word line, respectively.