Patents by Inventor Yasunori Hashimoto

Yasunori Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230370266
    Abstract: A token management system records consent of an end user who entrusts operation of a token to a blockchain network participant organization deploying a token based on a request from an end user. The system includes a token registration unit, a user management unit, a token management unit, a policy management unit, and a life cycle management unit. The token registration unit registers a test result, an electronic signature, and a hash of a token program in the memory device as repository information, the electronic signature and the hash being confirmation evidence. The user management unit records consent of the end user, as a trail, to entrust operation of the token to a virtual organization, and registers the consent in the memory device. The token management unit records consent of the end user, as a trail, to deploy the token, and registers the consent in the memory device.
    Type: Application
    Filed: September 7, 2021
    Publication date: November 16, 2023
    Inventors: Yuki KONDO, Yasunori HASHIMOTO, Tomokazu SAKAI, Taichi ISHIGURE
  • Publication number: 20230325822
    Abstract: A transaction has: lock release information; and a lock release condition. A first transaction has a record with a plurality of successive lock release conditions. A lock release condition of the first transaction includes public key information pertaining to an electronic signature different from the electronic signature of the issuer of the transaction. An asset/fund settlement device posts the first transaction in a ledger and determines executability of a second transaction issued after the first transaction by comparing, in accordance with the order of the plurality of successive lock release conditions, the lock release information and the lock release condition which have been posted in the ledger to lock release information and a lock release condition in a ledger of the second transaction. Thus, in a DvP transaction using electronic settlement, locked assets are safely returned, and deterioration in liquidity of assets/funds is avoided when the transaction is not established.
    Type: Application
    Filed: July 27, 2021
    Publication date: October 12, 2023
    Inventors: Suguru NAGAHORA, Nishio YAMADA, Yasunori HASHIMOTO, Tomokazu SAKAI, Kaiho FUKUCHI
  • Publication number: 20220148079
    Abstract: A settlement system having a settlement requesting device that has a processor and a memory; a settlement execution device that has a processor and a memory; and an electronic credit management device that manages electronic credits or debts, wherein the settlement requesting device issues a payment request in accordance with an electronic settlement medium, and the settlement execution device accepts the payment request in accordance with the settlement medium, causes the electronic credit management device to record the occurrence of a debt in accordance with the payment request, and transmits the settlement medium to a receiver.
    Type: Application
    Filed: February 21, 2020
    Publication date: May 12, 2022
    Applicant: HITACHI, LTD.
    Inventors: Yusuke JIN, Nishio YAMADA, Yasunori HASHIMOTO
  • Patent number: 10339035
    Abstract: A test DB data generation method for generating a database for testing, which approximates an existing database, the test DB data generation apparatus comprising: extracting distribution information of values of each column of the existing database; extracting column dependency information of the existing database; and generating test DB data based on the distribution information and the column dependency information.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 2, 2019
    Assignee: HITACHI, LTD.
    Inventors: Keishi Ooshima, Yasunori Hashimoto, Ryota Mibe, Hirofumi Danno, Kiyoshi Yamaguchi
  • Publication number: 20170140309
    Abstract: An attribute having influence on a business flow is automatically extracted among one or more attributes associated with the business flow when the business flow is restored based on history data of business performed on a business system. An event sequence variation indicating an order of an attribute name is calculated based on a chronological relation of an attribute value of a date and time from history data of the business configured with an attribute name and an attribute value of business, the number of appearances of each attribute value of each attribute other than a date and time is counted for each event sequence variation, event sequences that are similar in a distribution of the number of appearances are grouped, and business flows generated for respective groups are integrated.
    Type: Application
    Filed: November 7, 2016
    Publication date: May 18, 2017
    Applicant: HITACHI, LTD.
    Inventors: Yasunori HASHIMOTO, Ryota MIBE, Hirofumi DANNO, Katsumi KAWAI, Keishi OOSHIMA, Kiyoshi YAMAGUCHI, Makoto KIMURA
  • Publication number: 20170091082
    Abstract: A test DB data generation method for generating a database for testing, which approximates an existing database, the test DB data generation apparatus comprising: extracting distribution information of values of each column of the existing database; extracting column dependency information of the existing database; and generating test DB data based on the distribution information and the column dependency information.
    Type: Application
    Filed: September 23, 2016
    Publication date: March 30, 2017
    Applicant: Hitachi, Ltd.
    Inventors: Keishi Ooshima, Yasunori Hashimoto, Ryota Mibe, Hirofumi Danno, Kiyoshi Yamaguchi
  • Patent number: 9436713
    Abstract: A database analyzer includes a data sorting unit sorting a data group acquired from an analysis target database based on data values in a table column and storing it as analysis target data in a storage unit; a data pattern creation processing unit creating a group for each data value based on differences between the data values and storing a data pattern in the storage unit; a data pattern judgment processing unit for judging validity of the data pattern; and a data pattern transformation processing unit for reconstructing the data pattern with respect to constituent elements of each group included in the data pattern by transforming each group in accordance with a specified conversion rule for converting the constituent elements, which are conceptually similar to each other, into the same constituent element, and storing it in the storage unit if a negative result is obtained for the validity judgment.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: September 6, 2016
    Assignee: HITACHI, LTD.
    Inventors: Yasunori Hashimoto, Ryota Mibe, Kentaro Yoshimura, Hirofumi Danno, Sadahiro Ishikawa, Kiyoshi Yamaguchi
  • Publication number: 20160004968
    Abstract: A correlation rule analysis apparatus extracts data dependence relation and restriction conditions of database columns of a database from data stored in the database. The correction rule analysis apparatus includes a correlation rule extraction part which extracts information of simultaneous appearance relation of data among plural columns as correlation rules from inputted database table data, a correlation rule summarization part which summarizes or puts the extracted correlation rules together on the basis of specific community and a summarization result appropriateness judgment part which calculates usefulness indexes as the data dependence relation and the restriction conditions from appearance frequency and combination in the summarized correlation rules.
    Type: Application
    Filed: February 4, 2015
    Publication date: January 7, 2016
    Applicant: HITACHI, LTD.
    Inventors: Yasunori HASHIMOTO, Keishi OOSHIMA, Hirofumi DANNO, Ryota MIBE, Kiyoshi YAMAGUCHI
  • Patent number: 9015658
    Abstract: A device and method automatically generate a program for buffering differences based on characteristics of a component. A buffer program for buffering differences of the way to use a component during different software environments is automatically generated. The device includes a controller for executing automatic generation of the buffer program, a memory including control information and a processing program, an input device for inputting the processing content of the component, and an output device for outputting the automatically generated buffer program. The memory records a plurality of forms for buffering the component as the control information and the controller extracts characteristic information based on the processing content of the component and records the extracted characteristic information as control information in the memory, selects a specified form based on the characteristic information, and generates the buffer program based on the selected form and the characteristic information.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: April 21, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Yasunori Hashimoto, Ryota Mibe, Shuhei Nojiri, Sadahiro Ishikawa, Kiyoshi Yamaguchi, Kentaro Yoshimura
  • Publication number: 20150032708
    Abstract: A database analysis apparatus pays its attention to table columns more than two constituting a table among plural tables that a database holds, and analyzes automatically a dependence and a limitation condition that exist between the table columns from a tendency of appearance at the same time of data which each table column maintains, which comprises a data category calculation means to calculate a method of categorizing a data group from association rules generated from the data group of two or more table columns and an association rules reconstruction means to generate association rules of the best granularity by reconstructing the association rules based on the result of the above categorizing.
    Type: Application
    Filed: July 24, 2014
    Publication date: January 29, 2015
    Applicant: HITACHI, LTD.
    Inventors: Yasunori HASHIMOTO, Ryota MIBE, Kentaro YOSHIMURA, Hirofumi DANNO, Keishi OSHIMA, Sadahiro ISHIKAWA, Kiyoshi YAMAGUCHI
  • Publication number: 20140122445
    Abstract: A database analyzer includes a data sorting unit sorting a data group acquired from an analysis target database based on data values in a table column and storing it as analysis target data in a storage unit; a data pattern creation processing unit creating a group for each data value based on differences between the data values and storing a data pattern in the storage unit; a data pattern judgment processing unit for judging validity of the data pattern; and a data pattern transformation processing unit for reconstructing the data pattern with respect to constituent elements of each group included in the data pattern by transforming each group in accordance with a specified conversion rule for converting the constituent elements, which are conceptually similar to each other, into the same constituent element, and storing it in the storage unit if a negative result is obtained for the validity judgment.
    Type: Application
    Filed: October 23, 2013
    Publication date: May 1, 2014
    Applicant: Hitachi, Ltd.
    Inventors: Yasunori HASHIMOTO, Ryota MIBE, Kentaro YOSHIMURA, Hirofumi DANNO, Sadahiro ISHIKAWA, Kiyoshi YAMAGUCHI
  • Publication number: 20130125091
    Abstract: A device and method automatically generate a program for buffering differences based on characteristics of a component. A buffer program for buffering differences of the way to use a component during different software environments is automatically generated. The device includes a controller for executing automatic generation of the buffer program, a memory including control information and a processing program, an input device for inputting the processing content of the component, and an output device for outputting the automatically generated buffer program. The memory records a plurality of forms for buffering the component as the control information and the controller extracts characteristic information based on the processing content of the component and records the extracted characteristic information as control information in the memory, selects a specified form based on the characteristic information, and generates the buffer program based on the selected form and the characteristic information.
    Type: Application
    Filed: September 7, 2012
    Publication date: May 16, 2013
    Applicant: HITACHI, LTD.
    Inventors: Yasunori Hashimoto, Ryota Mibe, Shuhei Nojiri, Sadahiro Ishikawa, Kiyoshi Yamaguchi, Kentaro Yoshimura
  • Publication number: 20120266131
    Abstract: The present invention is provided to apply a screen mockup developed for prototyping, without any modification, to actual product development for which the architecture differs. An automatic program generation device has: a storage part 170 for storing a screen mockup program 1720, a component setup file 1730, and execution architecture definition information 1760, a storage part 160 for storing component data, a mockup design information analysis part 110 for generating component design information from the screen mockup program 1720 and the component setup file 1730 and configuring a program execution infrastructure from the execution architecture definition information 1760, a component architecture decision part 130 for selecting on the basis of the component design information a program code fragment, which operates on the configured program execution infrastructure, and a program code generation part 140 for generating a program code from the selected program code fragment.
    Type: Application
    Filed: February 8, 2012
    Publication date: October 18, 2012
    Applicant: HITACHI, LTD.
    Inventors: Shuhei Nojiri, Ryota Mibe, Yasunori Hashimoto, Sadahiro Ishikawa, Kiyoshi Yamaguchi
  • Patent number: 7999352
    Abstract: A semiconductor device equipped with a metal thin film resistor is disclosed. The semiconductor device includes a second interlayer insulating film formed on a first interlayer insulating film including a formation area of a wiring pattern. Connecting holes are formed in the second interlayer insulating film corresponding to both ends of the metal thin film resistor and the wiring pattern. An upper part of each connecting hole is formed in a taper shape. A sidewall is formed on the inner wall of each connecting hole. The metal thin film resistor is formed on the second interlayer insulating film between the connecting holes, inside of each connecting hole, and on the wiring pattern.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: August 16, 2011
    Assignee: Ricoh Company, Ltd.
    Inventors: Kimihiko Yamashita, Yasunori Hashimoto
  • Patent number: 7986028
    Abstract: A semiconductor device, includes a lower layer side insulation film; a wiring pattern formed on the lower layer side insulation film; a base insulation film formed on the lower layer side insulation film and the wiring pattern; and a plurality of metal thin film resistance elements formed on the base insulation film; wherein a connection hole is formed in the base insulation film on the wiring pattern; the wiring pattern and the metal thin film resistance element are electrically connected in the connection hole; the metal thin film resistance element has a belt shape part arranged separately from the connection hole and a connection part continuously formed with the belt shape part and connected to the wiring pattern in the connection hole; and the connection parts of at least two of the metal thin film resistance element are formed in the single connection hole with a gap in between said connection parts.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: July 26, 2011
    Assignee: Ricoh Company, Ltd.
    Inventors: Kimihiko Yamashita, Yasunori Hashimoto
  • Patent number: 7833844
    Abstract: A disclosed method of producing a semiconductor device includes the steps of (A) forming a gate electrode and a trimming fuse on a semiconductor substrate; (B) forming a side wall insulating film covering the gate electrode and the trimming fuse; (C) forming a conductive film on the side wall insulating film and patterning the conductive film to form an etching stop layer and a resistance element; (D) forming a side wall on the sides of the gate electrode; (E) repeating, one or more times, sub-steps of forming an interlayer insulating film and of forming an upper wiring layer, and then forming a passivation film; (F) removing the passivation film and the interlayer insulating film in the trimming opening forming area until the etching stop layer is exposed; and (G) forming the trimming opening by removing the etching stop layer in the trimming opening forming area.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: November 16, 2010
    Assignee: Ricoh Company, Ltd.
    Inventor: Yasunori Hashimoto
  • Patent number: 7741676
    Abstract: A semiconductor apparatus includes a cell section including at least two transistors. A layer interval insulation coat is formed at least overlying the gate electrode use polysilicon and the gate contact use polysilicon. A source electrode metal coat is formed overlying the semiconductor substrate and insulated from the gate electrode use polysilicon and the gate contact use polysilicon, and is electrically connected to the body diffusion layer and the source diffusion layer. A gate use connection hole is formed on the layer interval insulation coat overlying the gate contact use polysilicon. The gate use connection hole has a width larger than that of the trench. A gate electrode metal coat is formed on the gate use connection hole and the layer interval insulation coat. The polysilicon coat is formed at the same level or lower than the surface of the semiconductor substrate.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: June 22, 2010
    Assignee: Ricoh Company, Ltd.
    Inventor: Yasunori Hashimoto
  • Patent number: 7718502
    Abstract: A semiconductor apparatus includes a wiring pattern, an insulating film, and a thin-metal-film resistor element. The insulating film is formed on the wiring pattern having connection holes vertically penetrating there-through to expose part of the wiring pattern at bottom regions of the connection holes. The connection holes are arranged with a space there-between. The thin-metal-film resistor element is formed on the insulating film and extending to continuously overlay and contact surfaces of the insulating film, inner walls of the connection holes, and the wiring pattern at the bottom regions of the connection holes.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: May 18, 2010
    Assignee: Ricoh Company, Ltd.
    Inventors: Kimihiko Yamashita, Yasunori Hashimoto
  • Publication number: 20080100348
    Abstract: A semiconductor device, includes a lower layer side insulation film; a wiring pattern formed on the lower layer side insulation film; a base insulation film formed on the lower layer side insulation film and the wiring pattern; and a plurality of metal thin film resistance elements formed on the base insulation film; wherein a connection hole is formed in the base insulation film on the wiring pattern; the wiring pattern and the metal thin film resistance element are electrically connected in the connection hole; the metal thin film resistance element has a belt shape part arranged separately from the connection hole and a connection part continuously formed with the belt shape part and connected to the wiring pattern in the connection hole; and the connection parts of at least two of the metal thin film resistance element are formed in the single connection hole with a gap in between said connection parts.
    Type: Application
    Filed: September 21, 2006
    Publication date: May 1, 2008
    Inventors: Kimihiko Yamashita, Yasunori Hashimoto
  • Publication number: 20080090371
    Abstract: A semiconductor apparatus includes a wiring pattern, an insulating film, and a thin-metal-film resistor element. The insulating film is formed on the wiring pattern having connection holes vertically penetrating there-through to expose part of the wiring pattern at bottom regions of the connection holes. The connection holes are arranged with a space there-between. The thin-metal-film resistor element is formed on the insulating film and extending to continuously overlay and contact surfaces of the insulating film, inner walls of the connection holes, and the wiring pattern at the bottom regions of the connection holes.
    Type: Application
    Filed: November 14, 2007
    Publication date: April 17, 2008
    Inventors: Kimihiko Yamashita, Yasunori Hashimoto