Abstract: A ferroelectric memory device includes: a memory cell having a ferroelectric capacitor connected between a plate line and a bit line; a first node connected to the bit line through a charge transfer MISFET; a potential generation circuit that has a first capacitor having a first terminal connected to the first node and a first switching MISFET connected to a second terminal of the first capacitor, and is capable of setting the first node to a negative potential; and a sense amplifier connected to the second terminal of the first capacitor. When reading a charge stored in the ferroelectric capacitor, the potential generation circuit sets the first node at a negative potential and then sets the first switching MISFET to an off state, thereby setting the second terminal of the first capacitor to a floating state, and the sense amplifier amplifies a potential on the second terminal of the first capacitor in the floating state.

Abstract: A ferroelectric memory device includes: a first p-channel type MISFET connected between a first bit line and a first node; a second p-channel type MISFET connected between a second bit line and a second node; a first negative potential generation circuit connected to the first node; and a second negative potential generation circuit connected to the second node, wherein a gate terminal of the first p-channel type MISFET and the second node are connected to each other, and a gate terminal of the second p-channel type MISFET and the first node are connected to each other.

Abstract: A ferroelectric memory device, having: a first charge-transfer MISFET, connected between a first bit line and a first node; a second charge-transfer MISFET, connected between a second bit line and a second node; a first capacitance, connected to the first node; a second capacitance, connected to the second node; a first p-channel MISFET, connected between the first charge-transfer MISFET and the first node, and the gate electrode of which is connected to the second node; and a second p-channel MISFET, connected between the second charge-transfer MISFET and the second node, and the gate electrode of which is connected to the first node.

Abstract: A semiconductor memory device includes: a memory cell array with m memory cells arranged in a first direction and n memory cells arranged in a second direction in a grid, each memory cell having a capacitor part using a ferroelectric film, and also having a first terminal, a second terminal, and a third terminal; two or more first wirings connecting the first terminals of the m memory cells arranged in the first direction; two or more second wirings connecting the second terminals of the n memory cells arranged in the second direction; and two or more third wirings connecting the third terminals of the m memory cells, the third wirings including, from among unit blocks resulting from dividing the memory cell array into q sections in the first direction and r sections in the second direction, each unit block having s memory cells arranged in the first direction and t memory cells arranged in the second direction in a grid, first to t-th wiring parts connecting the s memory cells arranged in the first direction

Abstract: A semiconductor memory device having: a memory cell array with m memory cells arranged in a first direction and n memory cells arranged in a second direction in a grid, each memory cell having a capacitor part using a ferroelectric film, and also having a first terminal, a second terminal, and a third terminal; two or more first wirings connecting the first terminals of the m memory cells arranged in the first direction; two or more second wirings connecting the second terminals of the n memory cells arranged in the second direction; two or more third wirings connecting the third terminals of the m memory cells, and means for selecting a third wiring from among the third wirings, the third wiring being selected based on the result of calculation in an adder circuit and a subtractor circuit.

Abstract: A ferroelectric memory device includes memory cells using ferroelectric capacitors provided at intersections of local bit lines associated with a main bit line and word lines. The ferroelectric memory device includes: first and second local bit lines associated with a first main bit line; first and second connection transistors for connecting the first and second local bit lines to the first main bit line; first and second grounding transistors for grounding the first and second local bit lines; a first selection line that is commonly connected to gates of the first grounding transistor and the second connection transistor; and a second selection line that is commonly connected to gates of the first connection transistor and the second grounding transistor.

Abstract: A ferroelectric memory device being short in the bit line direction. The ferroelectric memory device is structured including a first word line extending in the first direction; a plurality of element regions arrayed in the first direction on both sides of the first word line; a plurality of ferroelectric capacitors connected to the respective element regions and driven by the first word line. Each of the element regions preferably has a stair-like shape when seen in a plane view and the first word line is preferably arranged bent between the element regions.

Abstract: A ferroelectric memory device, having: a first charge-transfer MISFET, connected between a first bit line and a first node; a second charge-transfer MISFET, connected between a second bit line and a second node; a first capacitance, connected to the first node; a second capacitance, connected to the second node; a first p-channel MISFET, connected between the first charge-transfer MISFET and the first node, and the gate electrode of which is connected to the second node; and a second p-channel MISFET, connected between the second charge-transfer MISFET and the second node, and the gate electrode of which is connected to the first node.

Abstract: A ferroelectric memory device including: a first bit line which extends, from one end toward another end thereof, in a first direction; a plurality of first memory cells, which are connected to the first bit line and store predetermined data; a second bit line which extends, from one end toward another end thereof, in a second direction, which is a direction substantially opposite to the first direction; a plurality of second memory cells, which are connected to the second bit line and store predetermined data; a sense amplifier, which is connected to the one end of the first bit line and the one end of the second bit line, and which amplifies data which have been stored at the first memory cells and the second memory cells; a latch circuit, which is connected to the other end of the first bit line, and which latches data that the sense amplifier has amplified; a data bus, which transfers data which are to be stored at the first memory cells and the second memory cells; and a first switch, which is connected

Abstract: A ferroelectric memory device includes: a first p-channel type MISFET connected between a first bit line and a first node; a second p-channel type MISFET connected between a second bit line and a second node; a first negative potential generation circuit connected to the first node; and a second negative potential generation circuit connected to the second node, wherein a gate terminal of the first p-channel type MISFET and the second node are connected to each other, and a gate terminal of the second p-channel type MISFET and the first node are connected to each other.

Abstract: A ferroelectric random access memory device, includes at least one bit line extending in a first direction; a plurality of first active regions, arranged in the first direction a predetermined distance from each other on one side of the bit line, each being connected to the bit line and a first ferroelectric capacitor; and a plurality of second active regions, arranged in the first direction a predetermined distance from each other on the other side of the bit line, each being connected to the bit line and a second ferroelectric capacitor, the first active regions partly overlapping, in the first direction, the second active regions respectively neighboring the first active regions, and being arranged a predetermined distance from the respective neighboring second active regions in a second direction crossing the first direction.

Abstract: A memory circuit includes a latch circuit having a first inverter and a second inverter, a first ferroelectric capacitor that gives a first capacitance to a power supply terminal of the first inverter, a second ferroelectric capacitor that gives a second capacitance different from the first capacitance to a power supply terminal of the second inverter, and a voltage source that starts supplying a drive voltage for driving the latch circuit to the power supply terminal of the first inverter to which the first capacitance is given and the power supply terminal of the second inverter to which the second capacitance is given.

Abstract: A ferroelectric memory device includes: a memory cell having a transistor and a ferroelectric capacitor connected in series between a bit line and a plate line, and a connecting section below the ferroelectric capacitor; a dummy cell having a transistor, a ferroelectric capacitor and a connecting section, wherein the dummy cell has an electrically disconnected section among the bit line, the transistor, the ferroelectric capacitor, the connecting section and the plate line.

Abstract: A ferroelectric memory device includes memory cells using ferroelectric capacitors provided at intersections of local bit lines associated with a main bit line and word lines. The ferroelectric memory device includes: first and second local bit lines associated with a first main bit line; first and second connection transistors for connecting the first and second local bit lines to the first main bit line; first and second grounding transistors for grounding the first and second local bit lines; a first selection line that is commonly connected to gates of the first grounding transistor and the second connection transistor; and a second selection line that is commonly connected to gates of the first connection transistor and the second grounding transistor.

Abstract: A ferroelectric memory device includes a main bit line, a plurality of local bit lines associated with the main bit line and disposed intersecting word lines, a plurality of first switching elements provided between the local bit lines and the main bit line, respectively, a plurality of memory cells provided at intersecting positions between the word lines and each of the plurality of local bit lines, and a plurality of redundant memory cells provided at intersecting positions between the main bit line and the word lines, wherein a malfunctioning memory cell is prohibited from operating and a redundant memory cell performs a substitute operation, and the plurality of first switching elements are operated such that the local bit line connected with the malfunctioning memory cell is connected to the main bit line.

Abstract: To provide laminated type semiconductor memory devices that can improve the yield of chips without complicating wirings and components. There are provided a plurality of laminated semiconductor chip layers, and chip selection pads provided on each of the chip layers, which are mutually connected across the chip layers, respectively, such that a chip selection signal for selecting each of the chip layers is commonly inputted in each of the chip layers. Each of the chip layers is equipped with program circuits each of which is capable of programming an output signal, and a chip selection judging circuit that judges a chip selection based on the chip selection signal and an output signal of the program circuit. As a result, address information can be set afterwards by the program circuit, such that one kind of chips may suffice in the chip manufacturing stage. Because the chip selection signal is inputted in the common chip selection pads, independent wirings for the respective chips are not required.

Abstract: A semiconductor memory device includes: a memory cell array with m memory cells arranged in a first direction and n memory cells arranged in a second direction in a grid, each memory cell having a capacitor part using a ferroelectric film, and also having a first terminal, a second terminal, and a third terminal; two or more first wirings connecting the first terminals of the m memory cells arranged in the first direction; two or more second wirings connecting the second terminals of the n memory cells arranged in the second direction; and two or more third wirings connecting the third terminals of the m memory cells, the third wirings including, from among unit blocks resulting from dividing the memory cell array into q sections in the first direction and r sections in the second direction, each unit block having s memory cells arranged in the first direction and t memory cells arranged in the second direction in a grid, first to t-th wiring parts connecting the s memory cells arranged in the first direction

Abstract: A ferroelectric memory device being short in the bit line direction. The ferroelectric memory device is structured including a first word line extending in the first direction; a plurality of element regions arrayed in the first direction on both sides of the first word line; a plurality of ferroelectric capacitors connected to the respective element regions and driven by the first word line. Each of the element regions preferably has a stair-like shape when seen in a plane view and the first word line is preferably arranged bent between the element regions.

Abstract: A ferroelectric random access memory device, includes at least one bit line extending in a first direction; a plurality of first active regions, arranged in the first direction a predetermined distance from each other on one side of the bit line, each being connected to the bit line and a first ferroelectric capacitor; and a plurality of second active regions, arranged in the first direction a predetermined distance from each other on the other side of the bit line, each being connected to the bit line and a second ferroelectric capacitor, the first active regions partly overlapping, in the first direction, the second active regions respectively neighboring the first active regions, and being arranged a predetermined distance from the respective neighboring second active regions in a second direction crossing the first direction

Abstract: A ferroelectric memory device including: a first bit line which extends, from one end toward another end thereof, in a first direction; a plurality of first memory cells, which are connected to the first bit line and store predetermined data; a second bit line which extends, from one end toward another end thereof, in a second direction, which is a direction substantially opposite to the first direction; a plurality of second memory cells, which are connected to the second bit line and store predetermined data; a sense amplifier, which is connected to the one end of the first bit line and the one end of the second bit line, and which amplifies data which have been stored at the first memory cells and the second memory cells; a latch circuit, which is connected to the other end of the first bit line, and which latches data that the sense amplifier has amplified; a data bus, which transfers data which are to be stored at the first memory cells and the second memory cells; and a first switch, which is connected