Abstract: To provide a storage circuit that can readily and stably read memory data, in storage circuits that are used mainly in program circuits. A storage circuit that is equipped with a flip-flop having a first terminal and a second terminal, a storage section having a first ferroelectric capacitor and a second ferroelectric capacitor for storing specified data, a control section that supplies a driving voltage to the flip-flop, and controls potentials on the first terminal and the second terminal based on the specified data, thereby retaining the specified data at the flip-flop, and a latch circuit that latches the specified data retained by the flip-flop based on potentials on the first terminal and the second terminal.

Abstract: A storage circuit equipped with a first ferroelectric capacitor and a second ferroelectric capacitor each having one end and another end, a first connecting section that is electrically connected to the one end of the first ferroelectric capacitor and the other end of the second ferroelectric capacitor, a second connecting section that is electrically connected to the other end of the first ferroelectric capacitor and the one end of the second ferroelectric capacitor, and a potential difference supply section that gives a predetermined potential difference between the one end of the first ferroelectric capacitor and the one end of the second ferroelectric capacitor. The potential difference supply section may preferably include a flip-flop having a first terminal and a second terminal.

Abstract: To provide laminated type semiconductor memory devices that can improve the yield of chips without complicating wirings and components. There are provided a plurality of laminated semiconductor chip layers, and chip selection pads provided on each of the chip layers, which are mutually connected across the chip layers, respectively, such that a chip selection signal for selecting each of the chip layers is commonly inputted in each of the chip layers. Each of the chip layers is equipped with program circuits each of which is capable of programming an output signal, and a chip selection judging circuit that judges a chip selection based on the chip selection signal and an output signal of the program circuit. The program circuit is equipped with writable nonvolatile memory cells, and a logical circuit that is connected to the nonvolatile memory cells and outputs a signal that is different depending on a recoded content in the nonvolatile memory cells, such that a step of melting fuses is not necessary.

Abstract: A memory circuit includes a latch circuit having a first inverter and a second inverter, a first ferroelectric capacitor that gives a first capacitance to a power supply terminal of the first inverter, a second ferroelectric capacitor that gives a second capacitance different from the first capacitance to a power supply terminal of the second inverter, and a voltage source that starts supplying a drive voltage for driving the latch circuit to the power supply terminal of the first inverter to which the first capacitance is given and the power supply terminal of the second inverter to which the second capacitance is given.

Abstract: A ferroelectric memory device includes a main bit line, a plurality of local bit lines associated with the main bit line and disposed intersecting word lines, a plurality of first switching elements provided between the local bit lines and the main bit line, respectively, a plurality of memory cells provided at intersecting positions between the word lines and each of the plurality of local bit lines, and a plurality of redundant memory cells provided at intersecting positions between the main bit line and the word lines, wherein a malfunctioning memory cell is prohibited from operating and a redundant memory cell performs a substitute operation, and the plurality of first switching elements are operated such that the local bit line connected with the malfunctioning memory cell is connected to the main bit line.

Abstract: To provide laminated type semiconductor memory devices that can improve the yield of chips without complicating wirings and components. There are provided a plurality of laminated semiconductor chip layers, and chip selection pads provided on each of the chip layers, which are mutually connected across the chip layers, respectively, such that a chip selection signal for selecting each of the chip layers is commonly inputted in each of the chip layers. Each of the chip layers is equipped with program circuits each of which is capable of programming an output signal, and a chip selection judging circuit that judges a chip selection based on the chip selection signal and an output signal of the program circuit. As a result, address information can be set afterwards by the program circuit, such that one kind of chips may suffice in the chip manufacturing stage. Because the chip selection signal is inputted in the common chip selection pads, independent wirings for the respective chips are not required.

Abstract: To provide laminated type semiconductor memory devices that can improve the yield of chips without complicating wirings and components. There are provided a plurality of laminated semiconductor chip layers, and chip selection pads provided on each of the chip layers, which are mutually connected across the chip layers, respectively, such that a chip selection signal for selecting each of the chip layers is commonly inputted in each of the chip layers. Each of the chip layers is equipped with program circuits each of which is capable of programming an output signal, and a chip selection judging circuit that judges a chip selection based on the chip selection signal and an output signal of the program circuit. The program circuit is equipped with writable nonvolatile memory cells, and a logical circuit that is connected to the nonvolatile memory cells and outputs a signal that is different depending on a recoded content in the nonvolatile memory cells, such that a step of melting fuses is not necessary.

Abstract: A storage circuit equipped with a first ferroelectric capacitor and a second ferroelectric capacitor each having one end and another end, a first connecting section that is electrically connected to the one end of the first ferroelectric capacitor and the other end of the second ferroelectric capacitor, a second connecting section that is electrically connected to the other end of the first ferroelectric capacitor and the one end of the second ferroelectric capacitor, and a potential difference supply section that gives a predetermined potential difference between the one end of the first ferroelectric capacitor and the one end of the second ferroelectric capacitor. The potential difference supply section may preferably include a flip-flop having a first terminal and a second terminal.

Abstract: To provide a storage circuit that can readily and stably read memory data, in storage circuits that are used mainly in program circuits. A storage circuit that is equipped with a flip-flop having a first terminal and a second terminal, a storage section having a first ferroelectric capacitor and a second ferroelectric capacitor for storing specified data, a control section that supplies a driving voltage to the flip-flop, and controls potentials on the first terminal and the second terminal based on the specified data, thereby retaining the specified data at the flip-flop, and a latch circuit that latches the specified data retained by the flip-flop based on potentials on the first terminal and the second terminal.

Abstract: To provide a storage circuit that can readily and stably read memory data, in storage circuits that are used mainly in program circuits. A storage circuit equipped with a flip-flop having a first terminal and a second terminal, a first ferroelectric capacitor that gives a first capacity to the first terminal, a second ferroelectric capacitor that gives a second capacity different from the first capacity to the second terminal, and a voltage source that starts supplying a driving voltage for driving the flip-flop to the flip-flop when the first capacity and the second capacity are given to the first terminal and the second terminal, respectively. Complementary data are preferably be written in the first ferroelectric capacitor and the second ferroelectric capacitor.