Patents by Inventor Yasunori Yamaguchi

Yasunori Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230117052
    Abstract: A control system includes: a first gateway device including: a virtual switch processor that connects a cloud virtual network to a wide area network and that configures a control virtual network within the cloud virtual network, and a first protocol converter that is connected to the wide area network and that converts communication data received from the cloud virtual network based on a proprietary protocol; and a second gateway device including: a second protocol converter that connects a local control network to the wide area network and that decodes the communication data received via the wide area network and converted by the first gateway device.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 20, 2023
    Applicant: YOKOGAWA ELECTRIC CORPORATION
    Inventors: Takumi Fujiwara, Yasunori Yamaguchi, Kyouko Yoshiwara
  • Patent number: 11149249
    Abstract: The present invention provides a base material for cell culture comprising a polyester resin comprising a dicarboxylic acid unit and a diol unit, wherein 1 to 80% by mol of the diol unit is a diol unit having a cyclic acetal structure.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: October 19, 2021
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Haruna Ando, Shin Iida, Yasunori Yamaguchi
  • Publication number: 20180265838
    Abstract: The present invention provides a base material for cell culture comprising a polyester resin comprising a dicarboxylic acid unit and a diol unit, wherein 1 to 80% by mol of the diol unit is a diol unit having a cyclic acetal structure.
    Type: Application
    Filed: September 23, 2016
    Publication date: September 20, 2018
    Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Haruna ANDO, Shin IIDA, Yasunori YAMAGUCHI
  • Publication number: 20180251733
    Abstract: The present invention provides a base material for cell culture comprising a polyester resin comprising a dicarboxylic acid unit and a diol unit, wherein 1 to 100% by mol of the diol units is a diol unit derived from 1,4-cyclohexanedimethanol.
    Type: Application
    Filed: September 23, 2016
    Publication date: September 6, 2018
    Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Haruna ANDO, Shin IIDA, Yasunori YAMAGUCHI
  • Patent number: 8360606
    Abstract: According to one embodiment, a light-emitting device includes a ceramic substrate, a plurality of light-emitting elements, and pressure member. The substrate includes a first surface in contact with a thermally radiative member, a second surface positioned in a side opposite to the first surface, and an outer circumferential surface which bridges outer circumferential edges of the first surface and the second surface. The light-emitting elements are mounted on the second surface of the substrate. The pressure member elastically press the substrate toward the thermally radiative member. A gap is provided between the pressure member and the outer circumferential surface of the substrate.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: January 29, 2013
    Assignees: Toshiba Lighting & Technology Corporation, Kabushiki Kaisha Toshiba
    Inventors: Haruki Takei, Seiko Kawashima, Tsuyoshi Oyaizu, Yasunori Yamaguchi
  • Publication number: 20120326355
    Abstract: A sulfur-containing material in a melt state is stored in material hopper heated to a temperature within a preset temperature range of which a lower limit is equal to or above a melting point of sulfur. The stored sulfur-containing material is sucked by pressure generators and pulled out into cylinders heated to a temperature within the preset temperature range. The pulled out sulfur-containing material is pushed out from the cylinders under pressure applied by the pressure generator, and thereafter, the resultant material is injected into mold heated to a temperature within the preset temperature range. An injection port of the mold after the sulfur-containing material is fully injected is closed. By stopping heating of the mold, the sulfur-containing material is slowly cooled. After that, a modified sulfur concrete substance formed by cooling and solidifying the sulfur-containing material is taken out from the mold.
    Type: Application
    Filed: July 9, 2012
    Publication date: December 27, 2012
    Applicants: FUJI CONCRETE INDUSTRY CO., LTD., NIPPON OIL CORPORATION
    Inventors: Minoru Kurakake, Masaaki Chatani, Yoshifumi Tominaga, Yasunori Yamaguchi
  • Patent number: 8235705
    Abstract: A sulfur-containing material in a melt state is stored in material hopper 1 heated to a temperature within a preset temperature range of which a lower limit is equal to or above a melting point of sulfur. The stored sulfur-containing material is sucked by pressure generators 2a, 2b and pulled out into cylinders 11a, 11b heated to a temperature within the preset temperature range. The pulled out sulfur-containing material is pushed out from the cylinders under predetermined pressure applied by the pressure generator, and thereafter, the resultant material is injected from injection port 24 into mold 5 having therein a cavity which can be hermetically sealed and the mold being heated to a temperature within the preset temperature range. The injection port of the mold after the sulfur-containing material is fully injected in the cavity is closed. By stopping heating of the mold, the sulfur-containing material injected in the cavity is slowly cooled.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: August 7, 2012
    Assignees: Nippon Oil Corporation, Fuji Concrete Industry Co., Ltd.
    Inventors: Minoru Kurakake, Masaaki Chatani, Yoshifumi Tominaga, Yasunori Yamaguchi
  • Patent number: 7945410
    Abstract: An average fault ratio is calculated from product characteristics of a product as a target of yield prediction, in order to predict yield accurately in the course of manufacturing the prediction target product. With respect to a reference product, whose wiring pattern is different from the prediction target product but manufactured by the same manufacturing process, a monthly electric fault density is calculated from actually measured data. Respective average fault ratios are obtained from product characteristics of the prediction target product and the reference product. A monthly electric fault density of the prediction target product is obtained by multiplying the monthly electric fault density of the reference product by the ratio of the average fault ratios. The yield is calculated by using the monthly electric fault density of the month in which a yield prediction target lot of the prediction target product was processed.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: May 17, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Natsuyo Morioka, Seiji Ishikawa, Katsumi Ikegaya, Yasunori Yamaguchi, Kazuo Ito, Yuichi Hamamura
  • Publication number: 20110064841
    Abstract: In the present invention, as a sulfur-containing material fully filled into a cavity of a mold body in which the inside of an outer mold having the cavity which can be hermetically sealed is heated to a temperature within a preset temperature range of which a lower limit is equal to or above a melting point of sulfur is cooled and contracted in the cavity, the sulfur-containing material stored in a filling tank in which a cover is attached to an upper end opening of filling tank, so that the inside of filling tank can be hermetically sealed, and also, the inside of filling tank is pressurized to a predetermined pressure, and the inside of filling tank is heated to a temperature within the preset temperature range, is replenished into the cavity by a pressure in filling tank to mold a modified sulfur concrete substance product.
    Type: Application
    Filed: November 17, 2010
    Publication date: March 17, 2011
    Applicants: NIPPON OIL CORPORATION, FUJI CONCRETE INDUSTRY CO., LTD.
    Inventors: Minoru Kurakake, Hideyuki Horii, Yoshifumi Tominaga, Yasunori Yamaguchi
  • Publication number: 20110063842
    Abstract: According to one embodiment, a light-emitting device includes a ceramic substrate, a plurality of light-emitting elements, and pressure member. The substrate includes a first surface in contact with a thermally radiative member, a second surface positioned in a side opposite to the first surface, and an outer circumferential surface which bridges outer circumferential edges of the first surface and the second surface. The light-emitting elements are mounted on the second surface of the substrate. The pressure member elastically press the substrate toward the thermally radiative member. A gap is provided between the pressure member and the outer circumferential surface of the substrate.
    Type: Application
    Filed: September 13, 2010
    Publication date: March 17, 2011
    Applicants: TOSHIBA LIGHTING & TECHNOLOGY CORPORATION, KABUSHIKI KAISHA TOSHIBA
    Inventors: HARUKI TAKEI, Seiko Kawashima, Tsuyoshi Oyaizu, Yasunori Yamaguchi
  • Publication number: 20110012289
    Abstract: A sulfur-containing material in a melt state is stored in material hopper 1 heated to a temperature within a preset temperature range of which a lower limit is equal to or above a melting point of sulfur. The stored sulfur-containing material is sucked by pressure generators 2a, 2b and pulled out into cylinders 11a, 11b heated to a temperature within the preset temperature range. The pulled out sulfur-containing material is pushed out from the cylinders under predetermined pressure applied by the pressure generator, and thereafter, the resultant material is injected from injection port 24 into mold 5 having therein a cavity which can be hermetically sealed and the mold being heated to a temperature within the preset temperature range. The injection port of the mold after the sulfur-containing material is fully injected in the cavity is closed. By stopping heating of the mold, the sulfur-containing material injected in the cavity is slowly cooled.
    Type: Application
    Filed: September 27, 2010
    Publication date: January 20, 2011
    Applicants: NIPPON OIL CORPORATION, FUJI CONCRETE INDUSTRY CO., LTD.
    Inventors: Minoru Kurakake, Masaaki Chatani, Yoshifumi Tominaga, Yasunori Yamaguchi
  • Patent number: 7514060
    Abstract: A method for producing a porous potassium carbonate, which comprises calcining potassium hydrogen carbonate crystals having a mean particle diameter of from 100 to 1,000 ?m at a temperature of the object to be calcined of from 100 to 500° C., while introducing a dry gas which has a dew point of not higher than 0° C. and a temperature of from 10 to 50° C.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: April 7, 2009
    Assignee: Asahi Glass Company, Limited
    Inventors: Hachiro Hirano, Yasunori Yamaguchi, Minako Okamura
  • Patent number: 7499340
    Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: March 3, 2009
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • Publication number: 20080205111
    Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.
    Type: Application
    Filed: January 9, 2008
    Publication date: August 28, 2008
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • Publication number: 20080140330
    Abstract: An average fault ratio is calculated from product characteristics of a product as a target of yield prediction, in order to predict yield accurately in the course of manufacturing the prediction target product. With respect to a reference product, whose wiring pattern is different from the prediction target product but manufactured by the same manufacturing process, a monthly electric fault density is calculated from actually measured data. Respective average fault ratios are obtained from product characteristics of the prediction target product and the reference product. A monthly electric fault density of the prediction target product is obtained by multiplying the monthly electric fault density of the reference product by the ratio of the average fault ratios. The yield is calculated by using the monthly electric fault density of the month in which a yield prediction target lot of the prediction target product was processed.
    Type: Application
    Filed: August 9, 2007
    Publication date: June 12, 2008
    Inventors: Natsuyo Morioka, Seiji Ishikawa, Katsumi Ikegaya, Yasunori Yamaguchi, Kazuo Ito, Yuichi Hamamura
  • Patent number: 7345929
    Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: March 18, 2008
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • Publication number: 20070242535
    Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.
    Type: Application
    Filed: March 7, 2007
    Publication date: October 18, 2007
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • Patent number: 7203101
    Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: April 10, 2007
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • Publication number: 20060228351
    Abstract: An object of the present invention is to provide a method for inducing differentiation and/or promoting proliferation of regulatory T cells, a method for suppressing the transendothelial cell migration of immunocytes, a method for suppressing immunity using these methods, and a pharmaceutical composition to be used for these methods. Provided are a method for inducing differentiation and/or promoting proliferation of regulatory T cells by causing CD52 agonists, including anti-CD52 antibodies, to act on CD52-expressing T cells, a method for suppressing the transendothelial cell migration of immunocytes, and a method for suppressing immunity using these methods.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 12, 2006
    Inventors: Junichi Masuyama, Tomoko Watanabe, Yoshiaki Soma, Yasunori Yamaguchi
  • Publication number: 20060120125
    Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.
    Type: Application
    Filed: January 12, 2006
    Publication date: June 8, 2006
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata