Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: A semiconductor memory device is provided with a memory portion, a logical operation circuit which receives the data signal read out from such memory portion and the input data signal to form data to be offered to such memory portion, and a gate circuit. In case a data input operation is required which eliminates the logical operation, the input data signal is fed not via the logical operation circuit, but via the gate circuit directly to the memory portion. The semiconductor memory device constructed as above permits a high speed operation and is suited for use as the memory for image processing.

Abstract: A semiconductor memory device is provided with a memory portion, a logical operation circuit which receives the data signal read out from such memory portion and the input data signal to form data to be offered to such memory portion, and a gate circuit. In case a data input operation is required which eliminates the logical operation, the input data signal is fed not via the logical operation circuit, but via the gate circuit directly to the memory portion. The semiconductor memory device constructed as above permits a high speed operation and is suited for use as the memory for image processing.

Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal.

Abstract: A semiconductor memory device is provided with a memory portion, a logical operation circuit which receives the data signal read out from such memory portion and the input data signal to form data to be offered to such memory portion, and a gate circuit. In case a data input operation is required which eliminates the logical operation, the input data signal is fed not via the logical operation circuit, but via the gate circuit directly to the memory portion. The semiconductor memory device constructed as above permits a high speed operation and is suited for use as the memory for image processing.

Abstract: A semiconductor memory device is provided with a memory portion, a logical operation circuit which receives the data signal read out from such memory portion and the input data signal to form data to be offered to such memory portion, and a gate circuit. In case a data input operation is required which eliminates the logical operation, the input data signal is fed not via the long logical operation circuit, but via the gate circuit directly to the memory portion. The semiconductor memory device constructed as above permits a high speed operation and is suited for use as the memory for image processing.

Abstract: A semiconductor memory device is provided with a memory portion, a logical operation circuit which receives the data signal read out from such memory portion and the input data signal to form data to be offered to such memory portion, and a gate circuit. In case a data input operation is required which eliminates the logical operation, the input data signal is fed not via the logical operation circuit, but via the gate circuit directly to the memory portion. The semiconductor memory device constructed as above permits a high speed operation and is suited for use as the memory for image processing.

Abstract: A semiconductor memory is provided with a first memory cell group, a second memory cell group, a first register for a serial output operation for holding information related to the first memory cell group, a second register for a serial output operation for holding information related to the second memory cell group, and transfer means for transferring information related to either the first or second memory cell group to either the first or second serial output register. By virtue of this arrangement, while the information transferred to the first serial output register is being serially output therefrom, information can simultaneously be transferred to the second serial output register by the transfer means.

Abstract: A half precharge type dynamic RAM has a pair of data lines to which a plurality of dynamic memory cells are coupled. The paired data lines are set in advance before a read operation at a reference potential which is equal to one half of the supply voltage. One of the paired data lines is switched to have a higher or lower level than the reference potential by the memory cell selected. The potential difference applied between the paired data lines is amplified by the operation of a sense amplifier. Here, an address selecting MOSFET in the memory cell has a gate capacitance which will undesirably couple a word line and the data lines. As a result, one of the data lines has its level changed in an undesired manner. The noise inparted between the paired data lines by such coupling noise components can be substantially neglected by adopting a dummy MOSFET which operates to impart coupling noise components corresponding to the noise components caused by the address selecting MOSFET gate capacitance.

Abstract: A single chip semiconductor memory device having an arithmetic circuit to conduct plural kinds of arithmetic operations and a mask control circuit for inhibiting a substantial change in data in memory irrespective of the operations of the arithmetic circuit when it is brought into a masking state. The semiconductor memory device takes a preset operation mode for receiving from the outside a control signal for the arithmetic circuit and the mask control circuit. This control signal for the arithmetic circuit and the mask control circuit, which is given to the semiconductor memory device when in the preset operation mode, is latched in the semiconductor memory device until the device is brought again into the preset operation mode.

Abstract: A protective circuit consisting of a resistor and MOSFET in a diode form and a switching element are connected to a bonding pad in order to prevent destruction of an internal circuit consisting of one or more MOSFETs. The switching element may consist of a parasitic MOSFET whose source and drain regions are formed by well regions. One of the well regions is connected to a semiconductor region as a guard ring.

Abstract: A semiconductor memory is provided in which a column decoder is used commonly for the random input and output and the serial input/output by providing both a signal path for transmitting signals in parallel to the data lines of a memory array and a latch circuit and a switch path for connecting said latch circuit and a serial input/output common data line in response to a selection signal generated by a shift register, and by feeding the output signal of a random input/output column decoder as an initial value to the individual bits of said shift register.

Abstract: A semiconductor memory for serially reading data of memory cells connected to the selected one word line based on the clock signal which defines a picture element and for writing the write data serially input to the latch circuit based on such clock signal to the memory cells, during the horizontal blanking time of a CRT monitor.

Abstract: A semiconductor memory device is provided with a memory portion, a logical operation circuit which receives the data signal read out from such memory portion and the input data signal to form data to be offered to such memory portion, and a gate circuit. In case a data input operation is required which eliminates the logical operation, the input data signal is fed not via the logical operation circuit, but via the gate circuit directly to the memory portion. The semiconductor memory device constructed as above permits a high speed operation and is suited for use as the memory for image processing.