Patents by Inventor Yasuo Itoh
Yasuo Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12099207Abstract: A virtual image display device includes: an image display element that displays an image to be displayed as a virtual image; a propagation optical system that propagates light from the image display element; and a light guide member that guides the light propagated by the propagation optical system. The light guide member includes: a light beam incident part that introduces light including image information from the propagation optical system into the light guide member; an image extractor that extracts the light including image information from an inside of the light guide member; and an image emitter that emits the light including image information to an outside of the light guide member. The propagation optical system includes one or more optical members each having a curved surface shape that is non-rotationally symmetric with respect to an optical axis.Type: GrantFiled: March 18, 2020Date of Patent: September 24, 2024Assignee: RICOH COMPANY, LTD.Inventors: Naoki Nakamura, Shiori Ohsugi, Shigenobu Hirano, Yasuo Katano, Kenji Kameyama, Norikazu Igarashi, Aino Hasegawa, Satomi Tanaka, Masahiro Itoh, Yoshifumi Sudoh, Susumu Momma, Shun Okazaki
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Patent number: 9568599Abstract: A radar signal processing device is provided, which performs a scan correlation in a polar coordinate system to secure accuracy of the scan correlation, and prevents a suppression of a target object moving at high speed due to the scan correlation. A polar coordinate correlator performs, in a polar coordinate system, a correlation between reception data and previous correlated data stored in a previous data storage. A trend curve calculating module calculates a trend curve of a distance-direction signal level of the reception data in the polar coordinate system. A target detecting module detects a target based on the signal level of the reception data and the trend curve. Further, the polar coordinate correlator changes the contents of the correlation of the reception data based on the target detection result from the target detecting module.Type: GrantFiled: February 5, 2013Date of Patent: February 14, 2017Assignee: Furuno Electric Co. Ltd.Inventors: Masahiro Nakahama, Yasuo Itoh
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Publication number: 20150054672Abstract: A radar signal processing device is provided, which performs a scan correlation in a polar coordinate system to secure accuracy of the scan correlation, and prevents a suppression of a target object moving at high speed due to the scan correlation. A polar coordinate correlator performs, in a polar coordinate system, a correlation between reception data and previous correlated data stored in a previous data storage. A trend curve calculating module calculates a trend curve of a distance-direction signal level of the reception data in the polar coordinate system. A target detecting module detects a target based on the signal level of the reception data and the trend curve. Further, the polar coordinate correlator changes the contents of the correlation of the reception data based on the target detection result from the target detecting module.Type: ApplicationFiled: February 5, 2013Publication date: February 26, 2015Applicant: Furuno Electric Co., Ltd.Inventors: Masahiro Nakahama, Yasuo Itoh
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Patent number: 7139201Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.Type: GrantFiled: October 6, 2005Date of Patent: November 21, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritome, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige
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Publication number: 20060114729Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.Type: ApplicationFiled: October 6, 2005Publication date: June 1, 2006Inventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritome, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige
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Patent number: 6967892Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.Type: GrantFiled: March 19, 2004Date of Patent: November 22, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritome, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige
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Patent number: 6853600Abstract: A dummy cell (reference electric potential generating circuit) DC has a paraelectric capacitor DCC1 and a ferro-electric capacitor DCC2. One end of the paraelectric capacitor DCC1 and one end of the ferro-electric capacitor DCC2 are commonly connected to a node N1. A dummy plate electric potential DPL1 is supplied to the other end of the paraelectric capacitor DCC1, and a dummy plate electric potential DPL2 is supplied to the other end of the ferro-electric capacitor DCC2. When data of a memory cell MC is read at a bit line (selective bit line) BL1, a reference electric potential is supplied to a bit line (reference bit line) BL2 from the dummy cell DC.Type: GrantFiled: October 15, 2003Date of Patent: February 8, 2005Assignee: Kabushiki Kaisha ToshibaInventor: Yasuo Itoh
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Publication number: 20040174747Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.Type: ApplicationFiled: March 19, 2004Publication date: September 9, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritomo, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige
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Patent number: 6781895Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.Type: GrantFiled: November 28, 2000Date of Patent: August 24, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritome, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige
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Publication number: 20040130928Abstract: A dummy cell (reference electric potential generating circuit) DC has a paraelectric capacitor DCC1 and a ferro-electric capacitor DCC2. One end of the paraelectric capacitor DCC1 and one end of the ferro-electric capacitor DCC2 are commonly connected to a node N1. A dummy plate electric potential DPL1 is supplied to the other end of the paraelectric capacitor DCC1, and a dummy plate electric potential DPL2 is supplied to the other end of the ferro-electric capacitor DCC2. When data of a memory cell MC is read at a bit line (selective bit line) BL1, a reference electric potential is supplied to a bit line (reference bit line) BL2 from the dummy cell DC.Type: ApplicationFiled: October 15, 2003Publication date: July 8, 2004Inventor: Yasuo Itoh
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Patent number: 6493267Abstract: A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuiType: GrantFiled: April 18, 2001Date of Patent: December 10, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Miyamoto, Yasuo Itoh, Yoshihisa Iwata
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Patent number: 6404274Abstract: There is provided an internal voltage generating circuit for outputting positive multi-level voltages by using a current addition type D/A conversion circuit, and suppressing increase of the pattern area of a resistor network even if the number of bits of a digital input increases.Type: GrantFiled: April 9, 1999Date of Patent: June 11, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Koji Hosono, Yasuo Itoh, Ken Takeuchi
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Publication number: 20010014033Abstract: A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuiType: ApplicationFiled: April 18, 2001Publication date: August 16, 2001Inventors: Junichi Miyamoto, Yasuo Itoh, Yoshihisa Iwata
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Patent number: 6259612Abstract: An internal voltage generator generates an internal voltage that is obtained by up-converting or down-converting an external power supply voltage. A resistor-voltage divider, having a plurality of resistors, outputs a first divided voltage that is obtained by dividing the internal voltage according to a resistance ratio of the resistors. A capacitor-voltage divider, having a plurality of capacitors connected in series between an output terminal of the internal voltage generator and a ground level, outputs a second divided voltage from the capacitors. A comparator compares a reference voltage and the first divided voltage for controlling the internal voltage generator according to a result of comparison. The comparator judges whether to halt operation of the internal voltage generator or not based on the result of comparison between the reference voltage and the first divided voltage while the internal voltage generator is operating.Type: GrantFiled: September 19, 2000Date of Patent: July 10, 2001Assignee: Kabushiki Kaisha ToshibaInventor: Yasuo Itoh
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Patent number: 6240018Abstract: A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuiType: GrantFiled: November 30, 1999Date of Patent: May 29, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Miyamoto, Yasuo Itoh, Yoshihisa Iwata
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Patent number: 6172911Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.Type: GrantFiled: April 1, 1999Date of Patent: January 9, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritome, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige
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Patent number: 6107658Abstract: In a NAND EEPROM using the local self-boosting system, an intermediate voltage which allows a memory cell adjacent to a selected memory cell to be turned on is applied to the control gate of the adjacent memory cell. As a result, even if the adjacent memory cell is in a normally-off state, the potential of a bit line can be transmitted to the adjacent memory cell. Thus, the reliability of the write inhibition in a non-selected NAND memory cell column is improved, while data can be written at random into a plurality of memory cells in a selected NAND memory cell column. When data is to be erased, an absolute value of an erasing voltage applied to a control gate can be less. As a result, data can be erased by a lower erasure voltage than that required in the conventional art. Consequently, the element refinement, the reliability and the yield can be further improved.Type: GrantFiled: December 22, 1999Date of Patent: August 22, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Yasuo Itoh, Koji Sakui
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Patent number: 6081454Abstract: A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific biasing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplying the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.Type: GrantFiled: September 2, 1998Date of Patent: June 27, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Kazunori Ohuchi, Tomoharu Tanaka, Yoshihisa Iwata, Yasuo Itoh, Masaki Momodomi, Fujio Masuoka
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Patent number: 6061289Abstract: A variable potential generating circuit includes a resistive potential divider circuit and first and second operational amplifiers. The resistive potential divider circuit includes a switching element and a current-scaling type digital/analog converter circuit connected in series between a power supply node and a ground node. The resistive potential divider circuit has a first node at which a divided potential obtained by resistive division of a variable potential to be output from a variable potential output node appears and a second node to which a virtual potential is applied. The first operational amplifier compares the divided potential of the first node with a reference potential to effect the feedback control for setting the variable output potential equal to the reference potential. The second operational amplifier compares the virtual potential of the second node with the reference potential to effect the feedback control for setting the virtual potential equal to the reference potential.Type: GrantFiled: September 28, 1999Date of Patent: May 9, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Yasuo Itoh, Sumio Tanaka
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Patent number: 6049494Abstract: A semiconductor memory device includes a memory cell array in which memory cell units are arranged in a matrix, each memory cell unit being constructed by connecting plural memory cells, each of which is electrically rewritable, a select gate connected to a select gate line for connecting a memory cell unit to a bitline, a precharge circuit connected to a first node of the bitline, for supplying a precharge voltage higher than an power supply voltage in programming of data, and a latch circuit connected to a second node of the bitline via a transfer gate for holding data to be programmed into a memory cell, wherein channels of the plurality of the memory cells constituting a selected memory cell unit are charged to the precharge voltage in programming of data.Type: GrantFiled: February 3, 1998Date of Patent: April 11, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Koji Sakui, Yasuo Itoh, Yoshihisa Iwata