Abstract: The semiconductor memory device of the present invention includes a memory cell having a floating gate and a control gate, for maintaining data by shifting the threshold value. In the test mode, the data read from the memory cell is verified by the verify circuit. If the result of verify is not approved, the writing of data is carried out again. The number of times of such writing is counted by the count circuit. In the data table, various correlations between the numbers of times of write and write voltages are stored. The write voltage data corresponding to the number of times of write from the count circuit is selectively output from the data table. The write voltage data is written in the memory element by the write circuit. The voltage at the other terminal of the voltage limiting circuit for varying the write voltage, is divided into several voltages, and thus the write voltage can be varied.

Abstract: In a NAND EEPROM using the local self-boosting system, an intermediate voltage which allows a memory cell adjacent to a selected memory cell to be turned on is applied to the control gate of the adjacent memory cell. As a result, even if the adjacent memory cell is in a normally-off state, the potential of a bit line can be transmitted to the adjacent memory cell. Thus, the reliability of the write inhibition in a non-selected NAND memory cell column is improved, while data can be written at random into a plurality of memory cells in a selected NAND memory cell column. When data is to be erased, an absolute value of an erasing voltage applied to a control gate can be less. As a result, data can be erased by a lower erasure voltage than that required in the conventional art. Consequently, the element refinement, the reliability and the yield can be further improved.

Abstract: A variable potential generating circuit includes a resistive potential divider circuit and first and second operational amplifiers. The resistive potential divider circuit includes a switching element and a current-scaling type digital/analog converter circuit connected in series between a power supply node and a ground node. The resistive potential divider circuit has a first node at which a divided potential obtained by resistive division of a variable potential to be output from a variable potential output node appears and a second node to which a virtual potential is applied. The first operational amplifier compares the divided potential of the first node with a reference potential to effect the feedback control for setting the variable output potential equal to the reference potential. The second operational amplifier compares the virtual potential of the second node with the reference potential to effect the feedback control for setting the virtual potential equal to the reference potential.

Abstract: A picture switching apparatus for executing a fade-out/fade-in processing between adjacent video recording files includes a multiplier for multiplying a decoded video data with a multiplication coefficient (1-km), a multiplier for multiplying an output data of a data output circuit with a multiplication coefficient km and a data synthesizer for summing results of multiplication from the respective multipliers. The picture switching apparatus thus constructed performs the fade-out/fade-in processing without modification of the original video data for fading processing, by controlling km at the junction between the files such that the mining ratio of the color data for fading to a decoded color data is gradually increased/decreased.

Abstract: An electrically erasable programmable read-only memory is disclosed which has programmable memory cells connected to parallel bit lines provided above a semiconductor substrate. The memory cells include NAND cell blocks each of which has a series array of memory cell transistors. Parallel word lines are connected to the control gates of the memory cell transistors, respectively. In a data write mode, a selection transistor in a certain NAND cell block including a selected memory cell is rendered conductive to connect the certain cell block to a corresponding bit line associated therewith. Under such a condition, electrons are tunnel-injected into a floating gate of the selected memory cell transistor, and the threshold value of the certain transistor is increased to be a positive value. A logical data is thus written in the selected memory cell transistor.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit, a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.

Abstract: A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element and a transistor charges the bit line and line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range.

Abstract: A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific basing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplied the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: The semiconductor memory device of the present invention includes a memory cell having a floating gate and a control gate, for maintaining data by shifting the threshold value. In the test mode, the data read from the memory cell is verified by the verify circuit. If the result of verify is not approved, the writing of data is carried out again. The number of times of such writing is counted by the count circuit. In the data table, various correlations between the numbers of times of write and write voltages are stored. The write voltage data corresponding to the number of times of write from the count circuit is selectively output from the data table. The write voltage data is written in the memory element by the write circuit. The voltage at the other terminal of the voltage limiting circuit for varying the write voltage, is divided into several voltages, and thus the write voltage can be varied.

Abstract: Memory cells each for storing 2-bit data are connected to a bit line. First and second flip-flop circuits are coupled to the bit line. The first flip-flop circuit holds the lower bit of 2-bit data read out from or written into the memory cell and the second flip-flop circuit holds the upper bit of 2-bit data read out from or written into the memory cell. At the data readout time, the upper bit is first read out from the memory cell and then the lower bit is read out from the memory cell. At the data writing time, the upper bit is first written into the memory cell and then the lower bit is written into the memory cell.

Abstract: A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A non-volatile semiconductor memory device including a plurality of bit lines; a plurality of word lines insulatively intersecting the bit lines; a memory cell array including a plurality of memory cells coupled to the bit lines and the word lines, each memory cell including a transistor with a charge storage portion; a plurality of programming circuits coupled to the memory cell array (i) for storing data which define whether or not write voltages are to be applied to respective of the memory cells, (ii) for selectively applying the write voltages to a part of the memory cells, which part is selected according to the data stored in the plurality of programing circuits, (iii) for determining actual written states of the memory cells, and (iv) for selectively modifying the stored data based on a predetermined logical relationship between the determined actual written states of the memory cells and the data stored in the plurality of programming circuits, thereby applying the write voltages only to memory cells

Abstract: A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range.

Abstract: An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence.