Abstract: A developing cartridge may include: a casing; a developing roller extending in a first direction; a developing-roller gear; a coupling including a coupling gear; a first idle gear; a second idle gear; an agitator; a first agitator gear; and a protrusion. The developing-roller gear, the coupling, the first idle gear, the second idle gear, the first agitator gear, and the protrusion may be positioned at an outer surface of the casing. The protrusion may be positioned between a first axis of the coupling and a third axis of the first agitator gear in a second direction connecting the first and third axes. The protrusion may be positioned outside an addendum circle of the developing-roller gear, an addendum circle of the coupling gear, an addendum circle of the first idle gear, and an addendum circle of the second idle gear. The first agitator gear may be spaced apart from the protrusion in the first direction.

Abstract: A connector (50) includes a tubular member (52) and a base tube (58). A light-guiding tube (60) is drawn out from the base tube (58) toward the opposite side to the tubular member (52). An adapter (1) includes: a first connecting portion (10) that can be connected to and disconnected from a light source device (70); a second connecting portion (20) that can be connected to and disconnected from the connector (50); and a light-guiding member (30) that guides light emitted from the light source device (70) to a proximal end surface (61) of the tube (60).

Abstract: A semiconductor circuit according to an embodiment of the present disclosure includes a nonvolatile latch circuit that stores k-bit data, and m-bit error correction data for the k-bit data.

Abstract: A semiconductor device capable of efficiently increasing a capacity of a mounted storage element while achieving space saving, and an electronic apparatus including this semiconductor device are provided. The semiconductor device includes a storage element including a filament that has a first conductive layer, a second conductive layer, and an insulation layer. The first conductive layer and the second conductive layer are stacked with at least the insulation layer interposed between the first conductive layer and the second conductive layer. The filament obtains at least three identifiable resistance states by changing a combination of a state of the first conductive layer, a state of the second conductive layer, and a state of the insulation layer. The semiconductor device further includes a writing unit that produces the at least three identifiable resistance states by applying a blow current to the storage element.

Abstract: A memory cell array unit according to an embodiment of the present disclosure includes a memory cell array and a microcontroller. The memory cell array includes an n-bit allocation bit allocated from a memory controller in read/write control, and a redundant bit of one or a plurality of bits not being provided with a switching mechanism that switches as a substitution for a portion of the allocation bit. The microcontroller reads and writes n-bit data from and into the memory cell array using the allocation bit and the redundant bit on the basis of the read/write control from the memory controller.

Abstract: A memory cell array unit according to an embodiment of the present disclosure includes a microcontroller that performs reading and writing from and into a memory cell array using n-bit allocation memory cells on the basis of read/write control from a memory controller. When a defect is found in one of the n-bit allocation memory cells, the microcontroller writes n?1-bit write data excluding data of a least significant bit among n-bit write data into n?1-bit allocation memory cells excluding the defective allocation memory cell among the n-bit allocation memory cells.

Abstract: A semiconductor apparatus includes a nonvolatile memory cell array including a plurality of first memory cells and a plurality of second memory cells including a first memory element 11 and a second memory element 12 including a resistance-variable nonvolatile memory element and a first selection transistor electrically connected to the first memory element 11 and the second memory element 12, in which a plurality of first memory elements 11 and a plurality of second memory elements 12 are arranged in a two-dimensional matrix in a first direction and a second direction different from the first direction and on the same interlayer insulating layer, the first memory element 11 is larger than the second memory element 12, and the first memory element 11 and the second memory element 12 are disposed adjacent to each other along the second direction.

Abstract: A semiconductor circuit according to the present disclosure includes: a first memory element including a first terminal, a second terminal coupled to a first node, and a tunnel barrier film, and configured to store information by breaking the tunnel barrier film; a first transistor including a drain coupled to the first node, a source, a gate, and a back gate coupled to a second node; and a second transistor including a drain, a source coupled to the second node, and a gate coupled to the first node.

Abstract: Provided is a semiconductor device having a structure suitable for higher integration. The semiconductor device includes a transistor that includes a gate section, a first diffusion layer, and a second diffusion layer. The semiconductor device further includes a first electrically-conductive section a second electrically-conductive section that is electrically insulated from the first electrically-conductive section, a first storage element that is located between the first diffusion layer and the first electrically-conductive section and is electrically coupled to each of the first diffusion layer and the first electrically-conductive section, and a second storage element that is located between the second diffusion layer and the second electrically-conductive section and is electrically coupled to each of the second diffusion layer and the second electrically-conductive section.

Abstract: A semiconductor circuit according to the present disclosure includes a first circuit that generates an inverted voltage of a voltage at a first node, and applies the inverted voltage to a second nodes, a second circuit that generates an inverted voltage of a voltage at the second node, and applies the inverted voltage to the first node, a first memory element that has a first terminal, a second terminal, and a third terminal, and stores information by setting a resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state in accordance with a direction of a first current flowing between the first terminal and the second terminal, a first transistor that couples the first node to the third terminal of the first memory element and a second transistor that is coupled to a first coupling node.

Abstract: A nonvolatile memory cell includes a resistance-change nonvolatile memory element 50 and a selection transistor TR. One end of the nonvolatile memory element 50 is connected to one source/drain region 15A of the selection transistor TR and is connected to a write line WR. The other source/drain region 15B of the selection transistor TR is connected to a select line SL. The other end of the nonvolatile memory element 50 is connected to a bit line BL.

Abstract: A semiconductor device capable of efficiently increasing a capacity of a mounted storage element while achieving space saving, and an electronic apparatus including this semiconductor device are provided. The semiconductor device includes a storage element including a filament that has a first conductive layer, a second conductive layer, and an insulation layer. The first conductive layer and the second conductive layer are stacked with at least the insulation layer interposed between the first conductive layer and the second conductive layer. The filament obtains at least three identifiable resistance states by changing a combination of a state of the first conductive layer, a state of the second conductive layer, and a state of the insulation layer. The semiconductor device further includes a writing unit that produces the at least three identifiable resistance states by applying a blow current to the storage element.

Abstract: A semiconductor circuit according to the present disclosure includes: a first memory element including a first terminal, a second terminal coupled to a first node, and a tunnel barrier film, and configured to store information by breaking the tunnel barrier film; a first transistor including a drain coupled to the first node, a source, a gate, and a back gate coupled to a second node; and a second transistor including a drain, a source coupled to the second node, and a gate coupled to the first node.

Abstract: A semiconductor circuit according to the present disclosure includes: a first circuit that generates an inverted voltage of a voltage at a first node, and applies the inverted voltage to a second node; a second circuit that generates an inverted voltage of a voltage at the second node, and applies the inverted voltage to the first node; a first memory element that has a first terminal, a second terminal, and a third terminal, and stores information by setting a resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state in accordance with a direction of a first current flowing between the first terminal and the second terminal; a first transistor that couples the first node to the third terminal of the first memory element by being turned on; and a second transistor that is coupled to a first coupling node being one of the first node and the second node, and causes the first current to flow to the second terminal of the first memory element on t

Abstract: A semiconductor circuit includes a first circuit to apply an inverted voltage of a voltage at a first node to a second node, a second circuit to apply an inverted voltage of a voltage at the second node to the first node, a first transistor that includes a gate, a drain, and a source, and stores a threshold state, a second transistor that couples the first node to a first terminal by being turned on, a third transistor that couples a first predetermined node to the gate of the first transistor, and a driving section that controls operations of the second transistor and the third transistor, and applies a control voltage to a second terminal. The first terminal is one of the drain or the source of the first transistor. The second terminal is another of the drain or the source of the first transistor.

Abstract: A volatile logic circuit has a storage node, and stores inputted information. A plurality of non-volatile elements are connected to the storage node of the volatile logic circuit through the same connection gate, and control lines for control for these non-volatile elements are connected to the respective non-volatile elements, every non-volatile element. A plurality of non-volatile elements are connected to the volatile logic circuit through the same connection gate in such a way, thereby enabling the yield to be enhanced.

Abstract: A semiconductor device having a structure suitable for higher integration is provided. The semiconductor device includes: a transistor including a gate section, a first diffusion layer, and a second diffusion layer; a first electrically-conductive section; a second electrically-conductive section that is electrically insulated from the first electrically-conductive section; a first storage element that is located between the first diffusion layer and the first electrically-conductive section and is electrically coupled to each of the first diffusion layer and the first electrically-conductive section; and a second storage element that is located between the second diffusion layer and the second electrically-conductive section and is electrically coupled to each of the second diffusion layer and the second electrically-conductive section.

Abstract: A semiconductor circuit includes first (IV1, IV3) and second (IV2, IV4) circuits, first (31) and second (32) transistors, a first storage element (35), and a driver (22, 23, 52, 53). The first (IV1, IV3) and second (IV2, IV4) circuits, respectively, apply inverted voltages of voltages at first (N1) and second (N2) nodes to the second (N2) and first (N1) nodes. The first transistor (31) is turned on to couple the first (N1) and third nodes. The second transistor (32) includes a gate coupled to the first node (N1), a drain and a source. One of the drain and the source is coupled to the third node, and another is supplied with a first control voltage (SCL1). The first storage element (35) includes a first end coupled to the third node and a second end supplied with a second control voltage (SCTRL). The first storage element (35) is able to take a first or second resistance state.

Abstract: A semiconductor circuit of the disclosure includes a first circuit that is able to generate, on the basis of a voltage at a first node, an inverted voltage of the voltage at the first node, and apply the inverted voltage to a second node, a second circuit that is able to generate, on the basis of a voltage at the second node, an inverted voltage of the voltage at the second node, and apply the inverted voltage to the first node, a first transistor that is turned ON to couple the first node to a third node, a second transistor that is turned ON to supply a first direct-current voltage to the third node, and a first storage section that is coupled to the third node and includes a first storage device that is able to take a first resistance state or a second resistance state.

Abstract: A semiconductor circuit according to the present disclosure includes: a first circuit that is configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit that is configured to apply an inverted voltage of a voltage at the second node to the first node; a first transistor that includes a gate, a drain, and a source, and is configured to store a threshold state; a second transistor that couples the first node to a first terminal by being turned on; a third transistor that couples a first predetermined node to the gate of the first transistor; and a driving section that controls operations of the second transistor and the third transistor, and applies a control voltage to a second terminal. The first terminal is one of the drain or the source of the first transistor. The first predetermined node is one of the first node or the second node. The second terminal is another of the drain or the source of the first transistor.