Abstract: The present disclosure relates to a semiconductor storage device, a driving method, and an electronic device capable of suppressing a layout area and improving reliability. A semiconductor storage device is provided with one or more selection transistors, a resistance change element one end of which is connected to a bit line and the other end of which is connected to a drain terminal of a selection transistor, the resistance change element a resistance value of which changes by a current of a predetermined value or larger allowed to flow, and a write control unit connected to a connection point between the selection transistor and the resistance change element and controls the current flowing through the resistance change element when data is written in the resistance change element. The present technology is applicable to, for example, a non-volatile memory provided with a storage element configured by a magnetic tunnel junction.

Abstract: A semiconductor circuit in the disclosure includes a first circuit that is able to generate, on the basis of a voltage in a first node, an inverted voltage of the voltage and to apply the inverted voltage to a second node; a second circuit that is able to generate, on the basis of a voltage in the second node, an inverted voltage of the voltage and to apply the inverted voltage to the first node; a first transistor that couples the first node to a third node; a second transistor that supplies a first direct-current voltage to the third node; a third transistor including a drain or a source to be coupled to the third node and including a gate coupled to the first node or the second node; and a first storage element that is coupled to the third node, and is able to take a first resistance state or a second resistance state. The first circuit and the second circuit are configured to cause the voltage in the first node to easily become a predetermined initial voltage after application of power.

Abstract: An object of the present technology is to improve the performance of a memory cell that stores the value reflecting the direction of an electric current. The memory cell includes an N-type transistor, a P-type transistor, and a storage element. The N-type transistor supplies a current either from a source to a drain thereof or from the drain to the source. The P-type transistor supplies a current from a source to a drain thereof. The storage element stores a logical value reflecting the direction of the current supplied from the drain of the N-type transistor and from the drain of the P-type transistor.

Abstract: A semiconductor circuit includes first (IV1, IV3) and second (IV2, IV4) circuits, first (31) and second (32) transistors, a first storage element (35), and a driver (22, 23, 52, 53). The first (IV1, IV3) and second (IV2, IV4) circuits, respectively, apply inverted voltages of voltages at first (N1) and second (N2) nodes to the second (N2) and first (N1) nodes. The first transistor (31) is turned on to couple the first (N1) and third nodes. The second transistor (32) includes a gate coupled to the first node (N1), a drain and a source. One of the drain and the source is coupled to the third node, and another is supplied with a first control voltage (SCL1). The first storage element (35) includes a first end coupled to the third node and a second end supplied with a second control voltage (SCTRL). The first storage element (35) is able to take a first or second resistance state.

Abstract: The present disclosure relates to a semiconductor storage device, a driving method, and an electronic device capable of suppressing a layout area and improving reliability. A semiconductor storage device is provided with one or more selection transistors, a resistance change element one end of which is connected to a bit line and the other end of which is connected to a drain terminal of a selection transistor, the resistance change element a resistance value of which changes by a current of a predetermined value or larger allowed to flow, and a write control unit connected to a connection point between the selection transistor and the resistance change element and controls the current flowing through the resistance change element when data is written in the resistance change element. The present technology is applicable to, for example, a non-volatile memory provided with a storage element configured by a magnetic tunnel junction.

Abstract: A semiconductor circuit in the disclosure includes a first circuit that is able to generate, on the basis of a voltage in a first node, an inverted voltage of the voltage and to apply the inverted voltage to a second node; a second circuit that is able to generate, on the basis of a voltage in the second node, an inverted voltage of the voltage and to apply the inverted voltage to the first node; a first transistor that couples the first node to a third node; a second transistor that supplies a first direct-current voltage to the third node; a third transistor including a drain or a source to be coupled to the third node and including a gate coupled to the first node or the second node; and a first storage element that is coupled to the third node, and is able to take a first resistance state or a second resistance state. The first circuit and the second circuit are configured to cause the voltage in the first node to easily become a predetermined initial voltage after application of power.

Abstract: A semiconductor circuit of the disclosure includes a first circuit that is able to generate, on the basis of a voltage at a first node, an inverted voltage of the voltage at the first node, and apply the inverted voltage to a second node, a second circuit that is able to generate, on the basis of a voltage at the second node, an inverted voltage of the voltage at the second node, and apply the inverted voltage to the first node, a first transistor that is turned ON to couple the first node to a third node, a second transistor that is turned ON to supply a first direct-current voltage to the third node, and a first storage section that is coupled to the third node and includes a first storage device that is able to take a first resistance state or a second resistance state.

Abstract: The present technology relates to a semiconductor device which enables yield to be enhanced. A volatile logic circuit has a storage node, and stores inputted information. A plurality of non-volatile elements are connected to the storage node of the volatile logic circuit through the same connection gate, and control lines for control for these non-volatile elements are connected to the respective non-volatile elements, every non-volatile element. A plurality of non-volatile elements are connected to the volatile logic circuit through the same connection gate in such a way, thereby enabling the yield to be enhanced. The present technology can be applied to a semiconductor device.

Abstract: An object of the present technology is to improve the performance of a memory cell that stores the value reflecting the direction of an electric current. The memory cell includes an N-type transistor, a P-type transistor, and a storage element. The N-type transistor supplies a current either from a source to a drain thereof or from the drain to the source. The P-type transistor supplies a current from a source to a drain thereof. The storage element stores a logical value reflecting the direction of the current supplied from the drain of the N-type transistor and from the drain of the P-type transistor.

Abstract: A semiconductor device includes: an electric fuse circuit including first electric fuses used as data bits and second electric fuses used as polarity bits; and a write circuit configured to selectively pass a current through the first electric fuses and the second electric fuses and thereby write data in the electric fuse circuit. The write circuit is configured to perform a first process when number of write bits included in write data is larger than a value obtained by dividing total number of bits in the write data by 2. The first process includes writing of inverted write data in a plurality of first electric fuses, and including writing of inversion data in one of the second electric fuses. The plurality of first electric fuses are part of the first electric fuses. The inverted write data is inverted data of the write data. The inversion data represents inversion.

Abstract: A memory element includes: an electrical fuse provided to be inserted between a first input node and a second input node; and an antifuse provided to be inserted between the second input node and a third input node. The third input node is configured to be a node to which a voltage is allowed to be applied separately from a voltage to be applied to the first input node.

Abstract: A semiconductor device includes: an electric fuse circuit including first electric fuses used as data bits and second electric fuses used as polarity bits; and a write circuit configured to selectively pass a current through the first electric fuses and the second electric fuses and thereby write data in the electric fuse circuit. The write circuit is configured to perform a first process when number of write bits included in write data is larger than a value obtained by dividing total number of bits in the write data by 2. The first process includes writing of inverted write data in a plurality of first electric fuses, and including writing of inversion data in one of the second electric fuses. The plurality of first electric fuses are part of the first electric fuses. The inverted write data is inverted data of the write data. The inversion data represents inversion.

Abstract: A semiconductor device has an electrical fuse element including: a first filament; a second filament connected to the first filament; and a series readout section connected to an end of the first filament opposite to another end of the first filament connected to the second filament, the series readout section reading series resistance of the first filament and the second filament.

Abstract: A memory element includes: an electrical fuse provided to be inserted between a first input node and a second input node; and an antifuse provided to be inserted between the second input node and a third input node. The third input node is configured to be a node to which a voltage is allowed to be applied separately from a voltage to be applied to the first input node.

Abstract: An electric fuse includes: a filament having a first conductive layer and a second conductive layer formed on the first conductive layer, wherein at least three discernible resistive states are generated in the filament by changing of a combination of a state of the first conductive layer and a state of the second conductive layer.

Abstract: An electric fuse includes: a filament having a first conductive layer and a second conductive layer formed on the first conductive layer, wherein at least three discernible resistive states are generated in the filament by changing of a combination of a state of the first conductive layer and a state of the second conductive layer.

Abstract: A semiconductor device has an electrical fuse element including: a first filament; a second filament connected to the first filament; and a series readout section connected to an end of the first filament opposite to another end of the first filament connected to the second filament, the series readout section reading series resistance of the first filament and the second filament.

Abstract: A portable water-purifying means comprising an oblong pump room containing a hand pump therein and an oblong water-purifying room containing a water-purifying means therein and being equipped on its upper side with a water outlet in a casing equipped with a water inlet. The pump room and the water-purifying room are arranged in parallel to each other with a partition separating the two rooms, and these rooms communicate with each other through a passage arranged on their bottom sides. The water inlet and the passage are provided respectively with check valves which operates to limit flow of water to the direction from the inlet to the water-purifying room.