Abstract: A nonvolatile semiconductor storage apparatus is provided. To a data node and a reference node, a first transistor and a second transistor are respectively connected. In a data state determining operation, in the case where voltage is applied to the data node and reference node, the first and second transistors operate as precharge transistors in a first operation mode, and operate as mirror transistors in a second operation mode. The first and second operation modes are switched.

Abstract: A nonvolatile semiconductor storage apparatus is provided. To a data node and a reference node, a first transistor and a second transistor are respectively connected. In a data state determining operation, in the case where voltage is applied to the data node and reference node, the first and second transistors operate as precharge transistors in a first operation mode, and operate as mirror transistors in a second operation mode. The first and second operation modes are switched.

Abstract: A memory array includes a resistive memory cell array having a first cell transistor and a resistance change element connected in series and a reference cell array having a second cell transistor and a resistance element connected in series. The second cell transistor of the reference cell array is connected to a reference source line, and the resistance element is connected to a reference bit line. A dummy memory cell is connected to the reference bit line in the memory cell array, and both ends of a resistance change element of the dummy memory cell are short-circuited through the reference bit line.

Abstract: A memory array includes a resistive memory cell array having a first cell transistor and a resistance change element connected in series and a reference cell array having a second cell transistor and a resistance element connected in series. The second cell transistor of the reference cell array is connected to a reference source line, and the resistance element is connected to a reference bit line. A dummy memory cell is connected to the reference bit line in the memory cell array, and both ends of a resistance change element of the dummy memory cell are short-circuited through the reference bit line.

Abstract: The demand for reducing the size and increasing the degree of integration of semiconductor memory devices has increased. In a semiconductor memory device, a smoothing capacitor which has to be provided therein for stabilizing a power supply voltage etc. is formed in an underlying layer of memory cells A and B to overlap the two memory cells A and B which are adjacent each other. Thus, an area occupied by the smoothing capacitor having a large capacity can be reduced to increase the degree of integration, and the smoothing capacitor having a large capacity can be provided in the semiconductor memory device.

Abstract: A semiconductor memory device includes a plurality of memory cells connected to a common bit line, a plurality of select lines each configured to select at least one of the memory cells, a plurality of drive circuits each configured to drive at least one of the select lines, a sense amplifier configured to amplify a voltage occurring at the bit line depending on data stored in the selected memory cell. A memory region where the memory cells are provided has a first region and a second region. When the first region is read, a larger number of the select lines are simultaneously driven by the corresponding common drive circuit than those in the second region, and a larger number of the memory cells are simultaneously selected than those in the second region.

Abstract: The demand for reducing the size and increasing the degree of integration of semiconductor memory devices has increased. In a semiconductor memory device, a smoothing capacitor which has to be provided therein for stabilizing a power supply voltage etc. is formed in an underlying layer of memory cells A and B to overlap the two memory cells A and B which are adjacent each other. Thus, an area occupied by the smoothing capacitor having a large capacity can be reduced to increase the degree of integration, and the smoothing capacitor having a large capacity can be provided in the semiconductor memory device.

Abstract: A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of the memory cells and each of the cell plate lines being connected to the memory cells of a corresponding one of the rows. Each of the memory cell arrays includes a plurality of word lines each of which corresponds to each of the rows of the memory cells in the memory cell array. The number of the memory cells connected to each of the cell plate lines is larger than the number of the memory cells connected to one of the word lines corresponding to the each of the cell plate lines.

Abstract: A syndrome generation section generates a syndrome from input data having d bits of data bits and k bits of parity bits. A syndrome table stores a syndrome pattern indicating that no error has occurred in the input data and syndrome patterns indicating an error position. A comparison section compares the syndrome generated by the syndrome generation section with the syndrome patterns in the syndrome table, outputs a match signal when a syndrome pattern matching the syndrome exists, and outputs a no-match signal when no syndrome pattern matching the syndrome exists. An error correction section corrects the error in the input data based on the match signal from the comparison section.

Abstract: A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of the memory cells and each of the cell plate lines being connected to the memory cells of a corresponding one of the rows. Each of the memory cell arrays includes a plurality of word lines each of which corresponds to each of the rows of the memory cells in the memory cell array. The number of the memory cells connected to each of the cell plate lines is larger than the number of the memory cells connected to one of the word lines corresponding to the each of the cell plate lines.

Abstract: A semiconductor memory device including a ferroelectric memory includes: a nonvolatile memory having higher data retention capability under high temperature than the ferroelectric memory; and a connection circuit for switching between connection and disconnection of the ferroelectric memory and the nonvolatile memory. The ferroelectric memory receives, through the connection circuit, at least part of data which is unique to the device and which has been written into the nonvolatile memory, and retains the received data.

Abstract: A semiconductor memory device is provided with plural memory cells, plural bit lines BL, each bit line being commonly connected to the plural memory cells that are arranged in the same row, plural word lines WL and plural plate lines CP, each word line and each plate line being commonly connected to the plural memory cells that are arranged in the same column, plural plate voltage supply lines CPS arranged in the column direction, and means for electrically connecting each of the plural plate voltage supply lines to each of the corresponding plural plate lines.

Abstract: A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.

Abstract: A semiconductor memory device is provided with plural memory cells, plural bit lines BL, each bit line being commonly connected to the plural memory cells that are arranged in the same row, plural word lines WL and plural plate lines CP, each word line and each plate line being commonly connected to the plural memory cells that are arranged in the same column, plural plate voltage supply lines CPS arranged in the column direction, and means for electrically connecting each of the plural plate voltage supply lines to each of the corresponding plural plate lines.

Abstract: Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

Abstract: A memory cell array is composed of a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a capacitor having a plate electrode connected to a common cell plate and a storage electrode; and a transistor provided between the storage electrode of the capacitor and a bit line, with a gate connected to a word line. A first amplifier amplifies an I/O line pair to a first voltage and a second voltage higher than the first voltage. A second amplifier amplifies a bit line pair to the first voltage and a third voltage higher than the second voltage. A switch element switches the connection relationship between the I/O line pair and the bit line pair among a connected state, a disconnected state and a transmission limited state in which the potential transmitted is limited.

Abstract: An object of the present invention is to provide, in an FeRAM memory device fixed to a cell plate, a memory device in which RES_N (source line) of a reset transistor for resetting a storage node has a low resistance. A memory cell (101) includes a ferroelectric capacitance, a first MOS transistor for selecting the memory cell, and a second MOS transistor which is a reset transistor for resetting the storage node. Potential is supplied to RES_N (source line) (impurity activation region) of the second MOS transistor through the following two conductive layers: an impurity activation region which is a conductive layer below an upper electrode of the ferroelectric capacitance, and a bit-line formation wiring layer making up a bit line BL. This configuration makes it possible to supply potential to RES_N (source line) with a low resistance and perform a stable operation.

Abstract: The present invention provides a ferroelectric semiconductor memory device in which the potential of data read out from a normal cell is compared with the reference level of a reference cell so as to determine whether the readout data is the “H” data or the “L” data, wherein since the reference cell is in the relaxed state when reading out data from the normal cell for the first time, the reference cell is reset before reading out data from the normal cell. Then, data is read out from the normal cell, and then the reference cell is reset. In second and subsequent data read operations of reading out data from a normal cell of another address, the reference cell is in the reset state, whereby the reference level is the same between the first data read operation and the second or subsequent data read operation. Thus, the reference level is always kept at a predetermined constant level when data is read out from normal cells.

Abstract: To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

Abstract: Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.