Abstract: A semiconductor memory device includes memory cell blocks (11) through (14) including a nonvolatile memory cell. The memory cell blocks (11) through (14) include chip-data storing regions (11b) through (14b) for storing chip data containing operation parameters of the semiconductor memory device and pass-flag storing regions (11c) through (14c) for storing pass flags which correspond to the respective chip-data storing regions and show the validity of the stored chip data. The chip-data storing regions store the same chip data.

Abstract: Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

Abstract: A semiconductor memory device having a semiconductor substrate includes a plurality of reference cells 4 and a plurality of bit lines 10. The reference cells 4 are formed in a region near the centerline of a predetermined region of the semiconductor substrate which is perpendicular to the bit lines 10. The bit lines 10 form pairs each composed of two adjacent bit lines. Two bit lines 10 in each pair have a first parallel state and a second parallel state in which positions of the two bit lines are reversed from the first parallel state. Each pair of bit lines 10 has at least one cross section 11 where one of the pair of bit lines 10 crosses the other, to switch between the first parallel state and the second parallel state. The cross section 11 is provided in the predetermined region of the semiconductor substrate such that the length of a bit line 10 in the first parallel state is equal to the length of the bit line 10 in the second parallel state. The semiconductor memory device is reduced in size.

Abstract: A semiconductor memory apparatus including a simple circuit configuration and is capable of randomly accessing fuse data. A fuse cell 30 including a fuse 31 is connected to a pair of bit lines of a memory circuit. The fuse 31 and a fuse data output circuit (which includes a resistor 32 and an inverter 33) are connected to a pair of bit lines BLT and BLB of the memory circuit through a fuse selection switch 34. By allowing a column decoder 12 for selecting a pair of bit lines of the memory cell to also function as a decoder circuit for selecting a fuse, the bit lines of the memory circuit can be used as signal lines for outputting fuse data, whereby the circuit size is reduced and the circuit area is reduced.

Abstract: To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

Abstract: A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.

Abstract: A semiconductor memory device includes memory cell blocks (11) through (14) including a nonvolatile memory cell. The memory cell blocks (11) through (14) include chip-data storing regions (11b) through (14b) for storing chip data containing operation parameters of the semiconductor memory device and pass-flag storing regions (11c) through (14c) for storing pass flags which correspond to the respective chip-data storing regions and show the validity of the stored chip data. The chip-data storing regions store the same chip data.

Abstract: A semiconductor memory apparatus is provided which has a simple circuit configuration and is capable of randomly accessing fuse data. In the semiconductor memory apparatus of the present invention, a fuse cell 30 including a fuse 31 is connected to a pair of bit lines of a memory circuit. The fuse 31 and a fuse data output circuit (which includes a resistor 32 and an inverter 33) are connected to a pair of bit lines BLT and BLB of the memory circuit through a fuse selection switch 34. In the semiconductor memory apparatus of the present invention, by allowing a column decoder 12 for selecting a pair of bit lines of the memory cell to also function as a decoder circuit for selecting a fuse, the bit lines of the memory circuit can be used as signal lines for outputting fuse data, whereby the circuit size is reduced and the circuit area is reduced.

Abstract: A ferroelectric memory device includes a plurality of bit line pairs, a plurality of sense amplifiers, a plurality of memory cells, a plurality of reference cells, and a control circuit. Each of the bit line pairs is composed of first and second bit lines. Each of the sense amplifiers amplifies a potential difference across the corresponding bit line pair. The memory cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. The reference cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. In addition, each of the reference cells on each of the bit line pairs retains data different from data of a reference cell on the adjacent bit line pair. The control circuit drives the sense amplifiers, the memory cells, and the reference cells. During the drive of the sense amplifier, the control circuit inactivates a reference word line connected to the reference cell.

Abstract: A semiconductor memory device having a semiconductor substrate includes a plurality of reference cells 4 and a plurality of bit lines 10. The reference cells 4 are formed in a region near the centerline of a predetermined region of the semiconductor substrate which is perpendicular to the bit lines 10. The bit lines 10 form pairs each composed of two adjacent bit lines. Two bit lines 10 in each pair have a first parallel state and a second parallel state in which positions of the two bit lines are reversed from the first parallel state. Each pair of bit lines 10 has at least one cross section 11 where one of the pair of bit lines 10 crosses the other, to switch between the first parallel state and the second parallel state. The cross section 11 is provided in the predetermined region of the semiconductor substrate such that the length of a bit line 10 in the first parallel state is equal to the length of the bit line 10 in the second parallel state. The semiconductor memory device is reduced in size.

Abstract: The present invention has a configuration with which the data “0” and the data “1” can be arbitrarily written to a reference cell capacitor for generating a reference potential, and comprises a non-volatile capacitor for storing the data to be written. This configuration makes the fine adjustment of the reference potential possible without a mask correction, which improves yield. The present invention also comprises a means of rewriting only the reference capacitors. By this configuration, the dispersion of the reference potential can be controlled, and yield is improved.

Abstract: To provide a ferroelectric storage device which can read all the quantities of charge (polarization quantity: 2Pr) accumulated in a ferroelectric during a writing operation. In the present invention, a bit line is recharged, a charge quantity required for recharging is detected, and the quantity is read on a sub bit line, thereby achieving a stable reading operation.

Abstract: A ferroelectric memory device includes a plurality of bit line pairs, a plurality of sense amplifiers, a plurality of memory cells, a plurality of reference cells, and a control circuit. Each of the bit line pairs is composed of first and second bit lines. Each of the sense amplifiers amplifies a potential difference across the corresponding bit line pair. The memory cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. The reference cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. In addition, each of the reference cells on each of the bit line pairs retains data different from data of a reference cell on the adjacent bit line pair. The control circuit drives the sense amplifiers, the memory cells, and the reference cells. During the drive of the sense amplifier, the control circuit inactivates a reference word line connected to the reference cell.

Abstract: To provide a ferroelectric storage device which can read all the quantities of charge (polarization quantity: 2Pr) accumulated in a ferroelectric during a writing operation. In the present invention, a bit line is recharged, a charge quantity required for recharging is detected, and the quantity is read on a sub bit line, thereby achieving a stable reading operation.

Abstract: Data can be read from a ferroelectric memory cell with stability in the event of deterioration on a ferroelectric constituting the memory cell. A pair of precharge transistors precharges a selected bit line BL/XBL to a second potential VDD. After a while, a word line selector activates a word line WL, a current mirror amplifier amplifies a difference in current, which is applied to the pair of precharge transistors, to a sub bit line SBL/XSBL, and data is read from the ferroelectric memory cell.

Abstract: Data can be read from a ferroelectric memory cell with stability in the event of deterioration on a ferroelectric constituting the memory cell. A pair of precharge transistors precharges a selected bit line BL/XBL to a second potential VDD. After a while, a word line selector activates a word line WL, a current mirror amplifier amplifies a difference in current, which is applied to the pair of precharge transistors, to a sub bit line SBL/XSBL, and data is read from the ferroelectric memory cell.

Abstract: In a semiconductor storage device, a dummy redundancy decision circuit detects the endpoint of redundancy decision made by a column redundancy decision circuit and outputs a end-of-redundancy-decision signal RED. Responsive to the signal RED, a control signal generator outputs normal and redundant column control signals NEN and REN to normal and redundant column decoders, respectively, based on a result of the redundancy decision made by the column redundancy decision circuit and represented by a signal XSYP. Accordingly, a time a normal column select signal Y is output to select a normal column and a time a redundant column select signal SY is output to select a redundant column are both later than a reference time by an interval of the same length. In addition, the interval between the end of data line pre-charging and the start of data line potential amplification can be shortened. As a result, data can be read out much faster.