Abstract: A semiconductor device includes: a printed wiring substrate; a semiconductor chip mounted on a first surface of the printed wiring substrate; a sealing resin sealing the semiconductor chip on the first surface of the printed wiring substrate; an electrode pad provided on a second surface on a side opposite to the first surface of the printed wiring substrate; an electrode terminal connected to the electrode pad and protruding from the second surface; and a metal layer provided on a surface of the electrode pad on the electrode terminal side or on the side opposite to the electrode terminal so as to straddle a boundary line of the bonding surface between the electrode terminal and the electrode pad which is at least a boundary line on a side facing an outside of a mounting region of the semiconductor chip.

Abstract: A semiconductor device includes: a substrate; a first semiconductor chip; a first adhesive layer; a second semiconductor chip; a second adhesive layer; and a spacer. The substrate has a first surface. The first semiconductor chip is provided above the first surface. The first adhesive layer is provided on a lower surface, which is opposed to the substrate, of the first semiconductor chip and contains a plurality of types of resins different in molecular weight. The second semiconductor chip is provided between the substrate and the first adhesive layer. The second adhesive layer covers surroundings of the second semiconductor chip in a view from a normal direction of a first surface, and contains at least one type of the resin lower in molecular weight than the other resins among the plurality of types of resins contained in the first adhesive layer. The spacer covers surroundings of the second adhesive layer in the view from the normal direction of the first surface.

Abstract: A semiconductor device includes a substrate and a semiconductor chip. The semiconductor chip includes a semiconductor element on a first surface thereof. The semiconductor chip is provided on the substrate such that a second surface thereof, which is opposite to the first surface, faces an upper surface of the substrate. A metal layer is provided between the second surface of the semiconductor chip and the upper surface of the substrate. A metal material, in which the range of ? rays is shorter than for single-crystal silicon, is used in the metal layer.

Abstract: According to one embodiment, a semiconductor device includes a first wiring layer that includes a first surface and a second surface opposite to the first surface, a first semiconductor element that is mounted on the first surface side of the first wiring layer, a conductive pillar that is provided on the first surface side of the first wiring layer and has a height equal to or greater than a thickness of the first semiconductor element, a second wiring layer that includes a third surface and a fourth surface opposite to the third surface, is provided on the conductive pillar, and joined to the conductive pillar on the fourth surface side, a second semiconductor element that is mounted on the third surface side of the second wiring layer and connected to the second wiring layer by a first bonding wire, a first sealing material for sealing the first surface of the first wiring layer, the first semiconductor element, the conductive pillar, and the fourth surface of the second wiring layer, and a second sealing

Abstract: A semiconductor device includes a substrate and a semiconductor chip. The semiconductor chip includes a semiconductor element on a first surface thereof. The semiconductor chip is provided on the substrate such that a second surface thereof, which is opposite to the first surface, faces an upper surface of the substrate. A metal layer is provided between the second surface of the semiconductor chip and the upper surface of the substrate. A metal material, in which the range of ? rays is shorter than for single-crystal silicon, is used in the metal layer.

Abstract: A semiconductor device includes a first substrate having a first face and a second face, a first semiconductor chip on the first face, a first wire which electrically connects the first semiconductor chip and the first substrate, a first resin which seals the first semiconductor chip and the first wire, a first metal bump on the second face, a second substrate below the first substrate, the second substrate having a third face and a fourth face, a second semiconductor chip on the third face and electrically connected to the first metal bump, a second wire which electrically connects the second semiconductor chip and the second substrate, a second resin between the second face and the third face, the second resin sealing the first metal bump, the second semiconductor chip and the second wire, and a second metal bump on the fourth face.

Abstract: In one embodiment, a semiconductor device has a substrate, a first semiconductor chip, an electrode, a first and second connection member, and a first and second sealing member. The electrode is disposed on the first semiconductor chip and contains Al. The first connection member electrically connects the electrode and the substrate and contains Au or Cu. The first sealing member seals the first semiconductor chip and the first connection member. One or more second semiconductor chips are stacked on the first sealing member. The second sealing member seals the first connection member, the one or more second semiconductor chips, and the one or more second connection members. A ratio of a total weight W1 of Cl ions and Br ions in the first sealing member to a weight W0 of resins of the substrate and the first sealing member is 7.5 ppm or lower.

Abstract: According to one embodiment, a semiconductor device includes a control element provided above a main surface of a substrate through a first adhesion layer, a second adhesion layer provided to cover the control element a first semiconductor chip provided on the second adhesion layer, a bottom surface area of the first semiconductor chip being larger than a top surface area of the control element, and at least one side of an outer edge of the control element projecting to an outside of an outer edge of the first semiconductor chip.

Abstract: A semiconductor package includes a semiconductor chip formed with a non-volatile semiconductor memory, a resin encapsulation that encapsulates the semiconductor chip, electrodes in a lattice (solder balls) formed and arrayed in a lattice on a bottom surface of the resin encapsulation. The solder balls include a signal electrode formed within the central region of the array and a dummy electrode formed outside the signal electrode.

Abstract: A semiconductor device includes a lead frame having an element support and a lead portion. The lead frame has an area from the element support to inner leads of the lead portion, which is formed flat. First and second semiconductor elements are stacked in order on a lower surface of the lead frame. Electrode pads of the first semiconductor element are connected to the inner leads via first metal wires. Ends of the first metal wires, which are connected to the first semiconductor element, are embedded in the second adhesive layer of the second semiconductor element.

Abstract: A semiconductor device includes a wring board having a first surface with external connection terminals and a second surface with internal connection terminals. On the second surface of the wiring board, a semiconductor chip having electrode pads is mounted. The electrode pads of the semiconductor chip and the internal connection terminals of the wiring board are electrically connected via connecting members. The external connection terminals are arranged along two opposite outer sides of the wiring board and each have a rectangular shape elongated in a direction toward the outer side.

Abstract: A semiconductor device includes a chip unit mounted on a wiring board. The chip unit includes of semiconductor chips having electrode pads and an interposer having test pads exposed and electrode pads wired from the test pads. The semiconductor chips and the interposer are stacked in a step-like shape so as to be positioned the interposer in an uppermost level. The electrode pads of the semiconductor chips and the interposer are electrically connected by first connecting members, and the electrode pads of the semiconductor chips or the interposer and the wiring board are electrically connected by second connecting members.

Abstract: A USB terminal having a conductor layer to be an input/output terminal of a USB connector is formed on a first principle surface of a circuit board. A memory element is mounted on a second principle surface at an opposite side of a terminal forming surface of the circuit board, and the memory element is sealed with a sealing resin. A semiconductor memory device as a USB memory main body is constituted by them. A USB memory is constituted by housing the USB memory main body inside of a USB connector case.

Abstract: A semiconductor package includes a semiconductor chip formed with a non-volatile semiconductor memory, a resin encapsulation that encapsulates the semiconductor chip, electrodes in a lattice (solder balls) formed and arrayed in a lattice on a bottom surface of the resin encapsulation. The solder balls include a signal electrode formed within the central region of the array and a dummy electrode formed outside the signal electrode.

Abstract: A semiconductor device includes a wring board having a first surface with external connection terminals and a second surface with internal connection terminals. On the second surface of the wiring board, a semiconductor chip having electrode pads is mounted. The electrode pads of the semiconductor chip and the internal connection terminals of the wiring board are electrically connected via connecting members. The external connection terminals are arranged along two opposite outer sides of the wiring board and each have a rectangular shape elongated in a direction toward the outer side.

Abstract: A semiconductor device includes a lead frame having an element support and a lead portion. The lead frame has an area from the element support to inner leads of the lead portion, which is formed flat. First and second semiconductor elements are stacked in order on a lower surface of the lead frame. Electrode pads of the first semiconductor element are connected to the inner leads via first metal wires. Ends of the first metal wires, which are connected to the first semiconductor element, are embedded in the second adhesive layer of the second semiconductor element.

Abstract: A lead frame has a plurality of first inner leads having distal end portions and parallel to each other, and a plurality of second inner leads having distal end portions opposing the distal end portions of the first inner leads, longer than the first inner leads, and parallel to each other. The semiconductor chip has a plurality of bonding pads arranged along one side of an element formation surface, and is mounted on the surfaces of the plurality of second inner leads using an insulating adhesive. The plurality of bonding wires include first bonding wires which electrically connect the distal end portions of the plurality of first inner leads to some of the plurality of bonding pads, and a plurality of second bonding wires which electrically connect the distal end portions of the plurality of second inner leads to the rest of the plurality of bonding pads.

Abstract: A USB terminal having a conductor layer to be an input/output terminal of a USB connector is formed on a first principle surface of a circuit board. A memory element is mounted on a second principle surface at an opposite side of a terminal forming surface of the circuit board, and the memory element is sealed with a sealing resin. A semiconductor memory device as a USB memory main body is constituted by them. A USB memory is constituted by housing the USB memory main body inside of a USB connector case.

Abstract: A semiconductor package includes a semiconductor chip formed with a non-volatile semiconductor memory, a resin encapsulation that encapsulates the semiconductor chip, electrodes in a lattice (solder balls) formed and arrayed in a lattice on a bottom surface of the resin encapsulation. The solder balls include a signal electrode formed within the central region of the array and a dummy electrode formed outside the signal electrode.

Abstract: A semiconductor package includes a semiconductor chip formed with a non-volatile semiconductor memory, a resin encapsulation that encapsulates the semiconductor chip, electrodes in a lattice (solder balls) formed and arrayed in a lattice on a bottom surface of the resin encapsulation. The solder balls include a signal electrode formed within the central region of the array and a dummy electrode formed outside the signal electrode.