Patents by Inventor Yasuo Takemoto

Yasuo Takemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070045873
    Abstract: A semiconductor memory card comprises a wiring substrate having input-output terminals for inputting and outputting a signal formed on its topside; a semiconductor memory chip connected to pads formed on a topside or an underside of the wiring substrate; wirings for plating for supplying electric power necessary for electrolytic plating, formed on the wiring substrate and cut at a side edge portion thereof; and a sealing resin for sealing the semiconductor memory chip on the wiring substrate and sealing the side edge portion of the wiring substrate and an end of at least one of the wirings for plating.
    Type: Application
    Filed: August 11, 2006
    Publication date: March 1, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yasuo Takemoto
  • Publication number: 20060261489
    Abstract: A plurality of external connection terminals are formed on one surface of a printed board. Solder resist is coated on the other surface of the printed board so as to have an opening therein in at least part of an outer periphery of the board. A memory chip is mounted on the other surface of the board. A molding resin is provided which composes a package of a semiconductor memory card by sealing the other surface side of the board so as to cover the solder resist and the memory chip.
    Type: Application
    Filed: May 22, 2006
    Publication date: November 23, 2006
    Inventors: Yasuo Takemoto, Naohisa Okumura, Taku Nishiyama
  • Publication number: 20050236698
    Abstract: A lead frame has a plurality of first inner leads having distal end portions and parallel to each other, and a plurality of second inner leads having distal end portions opposing the distal end portions of the first inner leads, longer than the first inner leads, and parallel to each other. The semiconductor chip has a plurality of bonding pads arranged along one side of an element formation surface, and is mounted on the surfaces of the plurality of second inner leads using an insulating adhesive. The plurality of bonding wires include first bonding wires which electrically connect the distal end portions of the plurality of first inner leads to some of the plurality of bonding pads, and a plurality of second bonding wires which electrically connect the distal end portions of the plurality of second inner leads to the rest of the plurality of bonding pads.
    Type: Application
    Filed: April 26, 2005
    Publication date: October 27, 2005
    Inventors: Isao Ozawa, Akihito Ishimura, Yasuo Takemoto, Tetsuya Sato