Patents by Inventor Yasushi Akao
Yasushi Akao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120023281Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.Type: ApplicationFiled: March 24, 2011Publication date: January 26, 2012Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito
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Publication number: 20100191934Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.Type: ApplicationFiled: March 18, 2010Publication date: July 29, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Patent number: 7558944Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.Type: GrantFiled: March 7, 2008Date of Patent: July 7, 2009Assignee: Renesas Technology Corp.Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
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Publication number: 20080313444Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.Type: ApplicationFiled: August 21, 2008Publication date: December 18, 2008Inventors: Shumpei KAWASAKI, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Publication number: 20080294873Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.Type: ApplicationFiled: March 7, 2008Publication date: November 27, 2008Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
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Publication number: 20080263228Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.Type: ApplicationFiled: May 5, 2008Publication date: October 23, 2008Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito
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Patent number: 7363466Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.Type: GrantFiled: February 14, 2006Date of Patent: April 22, 2008Assignee: Renesas Technology Corp.Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
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Publication number: 20060224859Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.Type: ApplicationFiled: February 14, 2006Publication date: October 5, 2006Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
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Patent number: 7069423Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.Type: GrantFiled: July 22, 2002Date of Patent: June 27, 2006Assignee: Hitachi, Ltd.Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
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Patent number: 7054990Abstract: The external storage device according to the present invention which uses a non-volatile semiconductor memory such as a flash memory is provided with plural areas which store user data, and restricts access to the user data from a host computer and also dynamically changes an area an access to which is to be restricted. Accordingly, the ease of use of the external storage device for the host computer is improved. Specifically, the interior of the flash memory is divided into a normal area not protected by a password or the like and a protected area protected by a password or the like. A microprocessor controls accesses to the normal area and the protected area in accordance with a command from the host computer. In addition, the host computer can access the protected area after passing through authentication using a password. Moreover, the host computer changes information indicative of the location of the protected area, thereby dynamically changing the protection area.Type: GrantFiled: August 10, 2000Date of Patent: May 30, 2006Assignee: Renesas Technology Corp.Inventors: Takayuki Tamura, Jun Kitahara, Toru Owada, Shinichi Sawamura, Takeshi Asahi, Nagamasa Mizushima, Takashi Totsuka, Yasushi Akao
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Patent number: 6996700Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.Type: GrantFiled: December 11, 2001Date of Patent: February 7, 2006Assignee: Renesas Technology Corp.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Publication number: 20050251651Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.Type: ApplicationFiled: May 3, 2005Publication date: November 10, 2005Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Patent number: 6889240Abstract: In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.Type: GrantFiled: October 29, 2003Date of Patent: May 3, 2005Assignee: Renesas Technology Corp.Inventors: Atsushi Kiuchi, Yuji Hatano, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
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Publication number: 20040199716Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.Type: ApplicationFiled: April 13, 2004Publication date: October 7, 2004Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito
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Patent number: 6748507Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.Type: GrantFiled: June 13, 2002Date of Patent: June 8, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito
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Patent number: 6735683Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.Type: GrantFiled: October 4, 2002Date of Patent: May 11, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito
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Publication number: 20040083250Abstract: In microcomputers and digital signal processorsin which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chipthis invention prevents an increase in the number of processing steps caused by differing types of data handled by the calculators, thereby enhancing the efficiency of the digital signal processing.Type: ApplicationFiled: October 29, 2003Publication date: April 29, 2004Applicant: Hitachi, Ltd.Inventors: Atsushi Kiuchi, Yuji Hatano, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
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Patent number: 6668266Abstract: In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.Type: GrantFiled: October 11, 2001Date of Patent: December 23, 2003Assignee: Hitachi, Ltd.Inventors: Atsushi Kiuchi, Yuji Hatano, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
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Publication number: 20030233527Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.Type: ApplicationFiled: October 4, 2002Publication date: December 18, 2003Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito
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Patent number: 6591294Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.Type: GrantFiled: July 30, 2001Date of Patent: July 8, 2003Assignee: Hitachi, Ltd.Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito