Patents by Inventor Yasushi Akao
Yasushi Akao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030046514Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.Type: ApplicationFiled: June 13, 2002Publication date: March 6, 2003Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito
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Publication number: 20020184472Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.Type: ApplicationFiled: July 22, 2002Publication date: December 5, 2002Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, HIronobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
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Patent number: 6434690Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3.Type: GrantFiled: January 11, 1999Date of Patent: August 13, 2002Assignee: Hitachi, Ltd.Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
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Publication number: 20020078325Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.Type: ApplicationFiled: December 11, 2001Publication date: June 20, 2002Applicant: Hitachi, Ltd.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Patent number: 6405302Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.Type: GrantFiled: April 14, 1999Date of Patent: June 11, 2002Assignee: Hitachi, Ltd.Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
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Patent number: 6367050Abstract: A semiconductor integrated circuit device comprising a one-chip microcomputer having a nonvolatile memory circuit to and from which write and read operations are carried out at high speed in keeping with the cycle time of the processor. Part of the memory circuit is set aside as a read-only area for accommodating a data processing program, and the rest of the memory is used to write and read data thereto and therefrom. With no need to optimize the assignments of the ROM and RAM parts in the memory circuit, the one-chip microchip is easy to design and manufacture with high productivity. With the program storage area established as desired, users enjoy more convenience use of the one-chip microcomputer than before.Type: GrantFiled: September 20, 1999Date of Patent: April 2, 2002Assignee: Hitachi, Ltd.Inventors: Yasushi Akao, Kenichi Kuroda
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Patent number: 6351788Abstract: A data processor including a central processing unit and a plurality of direct map cache memories (3, 4) has a plurality of area designating circuits (5, 6) for variably designating location and size of address area in the memory space managed the central processing unit and partially overlaps the address area designated by a plurality of area designating circuits. Thereby, the overlapped area (Eco) has a function as the 2-way set associative cache memory in combination with a plurality of cache memories. For the non-overlapping area, respective cache memory functions as the direct map cache memory. It is previously judged to attain the necessary data processing capability by arranging which processing routine to which address area and then executing such routine with what processing speed.Type: GrantFiled: June 10, 1999Date of Patent: February 26, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takanaga Yamazaki, Yasushi Akao, Keiichi Kurakazu, Masayasu Ohizumi, Takeshi Kataoka, Tatsuo Nakai, Mitsuhiro Miyazaki, Yosuke Murayama
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Publication number: 20020019841Abstract: In microcomputers and digital signal processorspin which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chippthis invention prevents an increase in the number of processing steps caused by differing types of data handled by the calculators, thereby enhancing the efficiency of the digital signal processing.Type: ApplicationFiled: October 11, 2001Publication date: February 14, 2002Applicant: Hitachi, Ltd.Inventors: Atsushi Kiuchi, Yuji Hatano, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
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Patent number: 6343357Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.Type: GrantFiled: August 3, 2000Date of Patent: January 29, 2002Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System, Ltd.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Publication number: 20020007430Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.Type: ApplicationFiled: July 30, 2001Publication date: January 17, 2002Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito
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Patent number: 6279063Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.Type: GrantFiled: December 10, 1999Date of Patent: August 21, 2001Assignee: Hitachi Ltd.Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito
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Patent number: 6272620Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.Type: GrantFiled: April 4, 2000Date of Patent: August 7, 2001Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System, Ltd.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Patent number: 6253308Abstract: A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.Type: GrantFiled: April 2, 1998Date of Patent: June 26, 2001Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System, Ltd.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Patent number: 6223265Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.Type: GrantFiled: November 13, 1998Date of Patent: April 24, 2001Assignee: Hitachi, Ltd.Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito
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Patent number: 6212620Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.Type: GrantFiled: November 13, 1998Date of Patent: April 3, 2001Assignee: Hitachi, Ltd.Inventors: Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito
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Patent number: 6205535Abstract: A branch instruction format has different respective field lengths for conditional branch instructions and unconditional branch instructions. A conditional branch instruction has a first bit length and a first area for a displacement designating an address to be jumped, wherein the first area has a second bit length that is smaller than the first bit length. An unconditional branch instruction also has the first bit length, and a second area for a displacement designating an address to be jumped, wherein the second area has a third bit length that is different from the first and second bit lengths.Type: GrantFiled: October 6, 1998Date of Patent: March 20, 2001Assignee: Hitachi, Ltd.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Patent number: 6131154Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.Type: GrantFiled: July 23, 1997Date of Patent: October 10, 2000Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System, Ltd.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Patent number: 6122724Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.Type: GrantFiled: February 16, 1999Date of Patent: September 19, 2000Assignee: Hitachi, Ltd.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Patent number: 6002856Abstract: A semiconductor integrated circuit device comprising a one-chip microcomputer having a nonvolatile memory circuit to and from which write and read operations are carried out at high speed in keeping with the cycle time of the processor. Part of the memory circuit is set aside as a read-only area for accommodating a data processing program, and the rest of the memory is used to write and read data thereto and therefrom. With no need to optimize the assignments of the ROM and RAM parts in the memory circuit, the one-chip microchip is easy to design and manufacture with high productivity. With the program storage area established as desired, users enjoy more convenience use of the one-chip microcomputer than before.Type: GrantFiled: December 1, 1998Date of Patent: December 14, 1999Assignee: Hitachi, Ltd.Inventors: Yasushi Akao, Kenichi Kuroda
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Patent number: 5991545Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.Type: GrantFiled: June 7, 1995Date of Patent: November 23, 1999Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System Ltd.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe