Abstract: A storage controller includes: an error information management section configured to manage information in a plurality of addresses of a memory; and a refresh object determination section configured to determine a refresh object address in the memory based on the error information.

Abstract: An error detection and correction unit includes: a first-code error detection section configured to detect whether or not each of a plurality of first code words in a second code word has an error, the second code word generated by encoding the plurality of first code words in chains and being a code word containing a plurality of partial data; and a second-code error correction section configured to correct the error in one partial data containing the first code word in which the error is detected of the plurality of partial data in the second code word, based on adjacent partial data adjacent to the one partial data.

Abstract: A controller includes: a low-level error correction section configured to execute low-level error correction in which an error in a code word is corrected with use of a predetermined decoding algorithm; and a high-level soft-decision error correction section configured to execute high-level soft-decision error correction in which the error in the code word is corrected with use of a high-level algorithm when the error correction by the low-level error correction section has failed, the high-level algorithm being a soft-decision decoding algorithm having higher error correction capability than error correction capability of the predetermined decoding algorithm.

Abstract: An error detection and correction apparatus includes a code word read-out unit to execute read processing to read out a code word including a plurality of code elements by detection of an erasure position as read data from a memory address and to execute re-read processing to read out the code word as re-read data from the memory address after a predetermined time is elapsed from the time to read out the read data; a timing control erasure position detection unit to detect a position of the code element having a value not matched as the erasure position in the code word by determining whether or not the value is matched per the code word in the read data and the re-read data; and an error correction unit to correct an error based on the erasure position in the code word where the erasure position is detected.

Abstract: A storage control apparatus includes a standard read request unit, an error correcting unit, and a high-accuracy read request unit. The standard read request unit is configured to issue a request for a read with standard accuracy to a read address in a memory. The error correcting unit is configured to perform error correction on the basis of an error correcting code and data returned by the memory in response to the read request with the standard accuracy. The high-accuracy read request unit is configured to issue, when an error incapable of being corrected by the error correction is caused, a request again for a read with higher accuracy than the standard accuracy to the read address.

Abstract: There is provided a memory control device, including a request determining unit that determines a type of a request, and a control unit that writes read data read from a memory cell array in the memory cell array in units of predetermined pages of the memory cell array when the request is a refresh request, and divides the page of write data into units of groups and writes the page of the write data in the memory cell array over twice or more when the request is a write request.

Abstract: Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not the read data matches the write data for each of a plurality of memory cells, a retry inhibiting unit that inhibits a retry process from being performed in a memory cell in which the read data matches the write data among the plurality of memory cells, and a retry control unit that designates at least some memory blocks among the plurality of memory blocks and simultaneously executes the retry process when the read data does not match the write data in any one of the plurality of memory cells in which all the write data is written.

Abstract: There is provided a storage control apparatus including a memory state acquisition unit acquiring a storage state of a memory associated with a write target, and an operation instruction generation unit generating an operation instruction of at least 2 bits per cell of the memory associated with the write target, from the acquired storage state and write data.

Abstract: There is provided a storage control device including a read processing unit that reads data and inversion state information indicating whether the data is in an inverted state or a non-inverted state from a specific region of a memory cell array that stores the data and the inversion state information with first intensity in association, and a write processing unit that writes data obtained by inverting the data and a state obtained by changing a state indicated by the inversion state information to an opposite state in the specific region with second intensity that is different from the first intensity.

Abstract: There is provided a memory control apparatus including: a pre-read processing section reading pre-read data from a data area to be written to before a write process in a predetermined data area of a memory cell array; a conversion determination section which, upon selectively allowing the pre-read data to transition to either a first conversion candidate or a second conversion candidate of the write data to be written in the write process, generates a determination result for selecting either of the candidates based on the larger of two values of which one is the number of bits transitioning from the first value to the second value and of which the other is the number of bits transitioning from the second value to the first value; and a conversion control section selecting either of the candidates in accordance with the determination result.

Abstract: A storage controlling apparatus includes a command decoder and command processing section. The command decoder decides whether or not a plurality of access object addresses of different commands included in a command string correspond to words different from each other in a same one of blocks of a memory cell array which have a common plate. The command processing section collectively and successively executes, when it is decided that the access object addresses of the commands correspond to the words different from each other in the same block of the memory cell array, those of operations in processing of the commands in which an equal voltage is applied as a drive voltage between the plate and a bit line.

Abstract: A storage control device includes a first rewriting section, a second rewriting section, and a first retry control section. The first rewriting section performs first rewrite to rewrite other of two binary values into a memory cell in which one of the two binary values is written. The second rewriting section performs second rewrite to rewrite the one of the two binary values into the memory cell in which the other of the two binary values is written. The first retry control section causes the memory cell that has undergone the first rewrite to be subjected to the second rewrite followed by the first rewrite again if an error occurs during the first rewrite.

Abstract: Disclosed herein is a storage controlling apparatus, including: a status acquisition section configured to acquire status including a number of times of execution of verification after writing into a memory from the memory; a history information retention section configured to retain a history of the status as history information in an associated relationship with each of predetermined regions of the memory; and a region selection section configured to select a region which satisfies a condition in accordance with the history information when a new region is to be used in the memory.

Abstract: Disclosed herein is a storage controlling apparatus including: a decision portion configured to decide whether or not a bit number of a specific value from between binary values is greater than a reference value in at least part of input data to a memory cell, which executes rewriting to one of the binary values and rewriting to the other one of the binary values in order in a writing process, to generate decision data indicative of a result of the decision; and a write side outputting portion configured to output, when it is decided that the bit number is greater than the reference value, the input data at least part of which is inverted as write data to the memory cell together with the decision data.

Abstract: Disclosed herein is a storage control apparatus including: a command processing section configured to receive a command requesting accesses to a plurality of access units by specifying an address in a memory space including a plurality of banks; and an address generating section configured to generate an address of an access unit serving as an object of the accesses in a bank selected from the banks as a bank determined in advance for the specified address.

Abstract: A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed.

Abstract: A state transition of a player operation is explicitly defined to facilitate the production of interactive contents. As a player model for reproducing a disk, a model including a player 300 for reproducing a stream, a platform 301 providing an interface between the player 300 and a hardware, and a script player 302 for realizing a scenario intended by a content producer is conceived. The states of the player 300 are defined by four states defined by combinations of two states as to whether the play list reproduction is performed or not and two states as to whether the command 311 is accepted or not. The state transition of the player 300 among the four states is generated by a method 313 from the script layer 302, but not by the player 300 itself or the command 311. The states of the player 300 are small in number, and the conditions for state transition are definite. Therefore, the interactive contents can be easily produced and mounted on devices.

Abstract: A data reproducing apparatus, which is capable of reproducing stream data according to time stamps without need to have an independent time counting clock. At step S141, it is determined whether a received access unit has a time stamp. When the access unit has a time stamp, the flow advances to step S142. At step S142, a value of the time stamp is set. When the access unit does not have a time stamp. The flow advances to step S144. At step S144, a value corresponding to the previous pic_struct is added to the current time. Thereafter, the flow advances to step S143. At step S143, the current pic_struct is stored for the next process. The present invention is capable of being applied to for example a game device using a DVD.

Abstract: A process corresponding to a reproduction time of data and an argument information is executed. When mark_time_stamp representing one reproduction time on a time axis of a play list, mark_type representing a type of Mark( ), and mark_type are of a type of an event that is generated, if a reproduction time of data reproduced corresponding to a play list containing PlayListMark( ) having Mark( ) including mark_data as an argument of the event matches mark_time_stamp, Mark( ) having mark_time_stamp is recognized at step S302. When mark_type of Mark( ) recognized represents a type in which the event is generated at step S307, mark_data of Mark( ) and occurrence of the event are notified at step S307. A process corresponding to mark_data is executed at step S308. The present invention can be applied to for example a game machine and so forth that use a DVD.

Abstract: A variable speed reproduction is accomplished without sacrifice of picture quality. A controller 425 creates EP_map( ) in a clip information file with an address of RAPI extracted by an RAPI information extraction unit 423, PTS of an intra-picture immediately preceded by RAPI, and one of end positions of the intra-picture and second, third, and fourth reference pictured preceded by the intra-picture and stores EP_map( ) to an output server 426. In other words, the controller 425 copies a value close to a predetermined sector count (the number of sectors that can be read at a time in the encode process) of the end positions of the four reference pictures (1stRef_picture, 2ndRef_picture, 3rdRef_picture, and 4thRef_picture) to N-th_Ref_picture_copy, decides index_minus1 based on N-th_Ref_picture_copy and records it on a disc.