Patents by Inventor Yasushi Koubuchi
Yasushi Koubuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8420527Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: August 3, 2011Date of Patent: April 16, 2013Assignee: Renesas Electronics CorporationInventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Publication number: 20110287595Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: August 3, 2011Publication date: November 24, 2011Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Patent number: 8022550Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: December 30, 2009Date of Patent: September 20, 2011Assignee: Renesas Electronics CorporationInventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Publication number: 20100096732Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: December 30, 2009Publication date: April 22, 2010Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Patent number: 7678684Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: July 26, 2007Date of Patent: March 16, 2010Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Patent number: 7626267Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: August 13, 2007Date of Patent: December 1, 2009Assignee: Renesas Technology CorporationInventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Patent number: 7554202Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: July 27, 2007Date of Patent: June 30, 2009Assignee: Renesas Technology CorpInventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Patent number: 7474003Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: May 23, 2007Date of Patent: January 6, 2009Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Publication number: 20080173973Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: August 13, 2007Publication date: July 24, 2008Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Publication number: 20080036091Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: July 26, 2007Publication date: February 14, 2008Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Publication number: 20080017990Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: July 27, 2007Publication date: January 24, 2008Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Publication number: 20070222001Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: May 23, 2007Publication date: September 27, 2007Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Patent number: 7274074Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: July 14, 2003Date of Patent: September 25, 2007Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Patent number: 7250682Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: October 4, 2004Date of Patent: July 31, 2007Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Patent number: 7199432Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: August 26, 2004Date of Patent: April 3, 2007Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Patent number: 7187039Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: April 8, 2005Date of Patent: March 6, 2007Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Patent number: 7163870Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: September 29, 2004Date of Patent: January 16, 2007Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Publication number: 20050179110Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: April 8, 2005Publication date: August 18, 2005Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Publication number: 20050040538Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: October 4, 2004Publication date: February 24, 2005Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
-
Publication number: 20050040537Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: September 29, 2004Publication date: February 24, 2005Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda