Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A thin film forming method and apparatus, wherein a negative voltage is applied alternately to a target and a substrate to perform film formation and reverse sputter alternately. Further, a coil is mounted between the target and the substrate and a high frequency current is made to flow therethrough to generate plasma. A negative base voltage smaller in absolute value than that during sputter may be applied to the substrate to make Ar ions flow into the substrate while it is subjected to reverse sputter. Thus, a film whose step coverage is 0.3 or more is possible. It becomes also possible to maintain a stable discharge and perform reverse sputter in a high vacuum region. The pressure of an Ar atmosphere may be lowered to 10.sup.-3 Torr or less. An aluminum wiring film whose peak value of x-ray diffraction strength at a (111) plane is 150 Kcps or more is possible.

Abstract: A semiconductor device having a high reliability wiring conductor structure applicable to DRAMs and SRAMs.The semiconductor device of the present invention is characterized by comprising a first wiring conductor film wherein a specific resistance is 5.about.15.mu..OMEGA.cm and an allowable current density is 1.times.10.sup.6 .about.1.times.10.sup.8 A/cm.sup.2 ; a second wiring conductor film having a laminated layer structure formed of a layer of high fusing point and low resistance material and a layer of an Al based alloy; and a plug composed of a high fusing point and low resistance material, electrically connecting to the first wiring conductor film and the second wiring conductor film. Thus, a semiconductor device showing almost no increase in electrical resistance in a wiring conductor film due to electromigration even after subjecting to a large current is provided.

Abstract: A semiconductor device and the method of fabricating the semiconductor device include a semiconductor substrate and a plurality of conductor films formed on the substrate. Each of the conductor films is made of aluminum alloy including at least one element selected from palladium and platinum and, more preferably, further including at least one element selected from lithium, beryllium, magnesium, manganese, iron, cobalt, nickel, copper, lanthanum, cerium, chromium hafnium, zirconium, cadmium, titanium, tungsten, vanadium, tantalum, and niobium, with a protective film which includes oxide of the selected one of palladium and platinum being formed on the side wall of the conductor film.

Abstract: A thin film forming method and apparatus is provided, wherein a negative voltage is applied alternately to a target and a substrate to perform film formation and reverse sputter alternately. Further, a coil is mounted between the target and the substrate and a high frequency current is made to flow therethrough to generate plasma. A negative base voltage smaller in absolute value than that during sputter may be applied to the substrate to make a fraction of Ar ions to flow into the substrate while it is subjected to reverse sputter. Thus, a film whose step coverage is 0.3 or more is possible. It becomes also possible to hold stable discharge and reverse sputter at a high vacuum region. The pressure of an Ar atmosphere may be lowered to 10.sup.-3 Torr or less. A film whose peak value of x-ray diffraction strength in the (111) plane is 150 Xcps or more is possible.

Abstract: This invention provides a semiconductor device having an electrode conductor layer on a semiconductor substrate through the medium of a diffusion barrier layer, comprising the diffusion barrier layer formed of an amorphous material having a higher crystallization temperature than the heat treatment temperature for the semiconductor device. According to this invention, the reaction between the metal conductor and the semiconductor substrate and the diffusion of the conductor material into the semiconductor substrate can be prevented and resultantly a semiconductor device having a high thermal reliability can be obtained.