Patents by Inventor Yasushi Nagadomi
Yasushi Nagadomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170076804Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.Type: ApplicationFiled: November 28, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventor: Yasushi NAGADOMI
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Patent number: 9583200Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.Type: GrantFiled: March 18, 2016Date of Patent: February 28, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Yasushi Nagadomi
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Publication number: 20160365154Abstract: A semiconductor memory device includes a memory cell, a sense amplifier connected to the memory cell, a first data latch that is connected to the sense amplifier and stores data of the memory cell, a second data latch that is connected to the sense amplifier and stores data of the memory cell, a third data latch that is connected to an input/output circuit, a fourth data latch that is connected to the input/output circuit, a first data bus of n-bit width that connects the sense amplifier, the first data latch, and the second data latch, and a second data bus of m-bit width that connects the third data latch and the fourth data latch to the first data bus, where m<n.Type: ApplicationFiled: March 3, 2016Publication date: December 15, 2016Inventors: Yasushi NAGADOMI, Satoru HOSHI
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Patent number: 9502116Abstract: According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality of bit lines. The row decoder applies a voltage to the first and second select transistors. The controller detects a defect of the bit lines based on data read from the memory cells.Type: GrantFiled: December 23, 2014Date of Patent: November 22, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Naoya Tokiwa, Yasushi Nagadomi
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Publication number: 20160203869Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.Type: ApplicationFiled: March 18, 2016Publication date: July 14, 2016Applicant: Kabushiki Kaisha ToshibaInventor: Yasushi NAGADOMI
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Publication number: 20160147455Abstract: A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.Type: ApplicationFiled: February 1, 2016Publication date: May 26, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yasushi NAGADOMI
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Patent number: 9330772Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.Type: GrantFiled: June 24, 2015Date of Patent: May 3, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Yasushi Nagadomi
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Patent number: 9280461Abstract: A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.Type: GrantFiled: July 18, 2014Date of Patent: March 8, 2016Assignee: Kabushiki Kaisha ToshibaInventor: Yasushi Nagadomi
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Publication number: 20150294728Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.Type: ApplicationFiled: June 24, 2015Publication date: October 15, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yasushi NAGADOMI
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Patent number: 9075740Abstract: A memory system (10) is disclosed, which comprises a flash-EEPROM nonvolatile memory (11) having a plurality of memory cells that have floating gates and in which data items are electrically erasable and writable, a cache memory (13) that temporarily stores data of the flash-EEPROM nonvolatile memory (11), a control circuit (12, 14) that controls the flash-EEPROM nonvolatile memory (11) and the cache memory (13), and an interface circuit (16) that communicates with a host, in which the control circuit functions to read data from a desired target area to-be-determined of the flash-EEPROM nonvolatile memory and detect an erased area to determine a written area/unwritten area by using as a determination condition whether or not a count number of data “0” of the read data has reached a preset criterion count number.Type: GrantFiled: June 4, 2014Date of Patent: July 7, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasushi Nagadomi, Daisaburo Takashima, Kosuke Hatsuda
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Patent number: 9076536Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.Type: GrantFiled: November 29, 2013Date of Patent: July 7, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Yasushi Nagadomi
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Publication number: 20150117102Abstract: According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality of bit lines. The row decoder applies a voltage to the first and second select transistors. The controller detects a defect of the bit lines based on data read from the memory cells.Type: ApplicationFiled: December 23, 2014Publication date: April 30, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoya TOKIWA, Yasushi NAGADOMI
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Publication number: 20150070993Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a memory string including a first memory cell and a second memory cell; a first word line connected to a gate of the first memory cell; a second word line connected to a gate of the second memory cell; and a peripheral circuit configured to control a write sequence and a read sequence, the peripheral circuit, during the write sequence or the read sequence on the first memory cell, executing a first operation on the condition that a positive first pass voltage is applied to the first word line and the second word line.Type: ApplicationFiled: March 13, 2014Publication date: March 12, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yasushi NAGADOMI
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Patent number: 8947933Abstract: According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality of bit lines. The row decoder applies a voltage to the first and second select transistors. The controller detects a defect of the bit lines based on data read from the memory cells.Type: GrantFiled: June 7, 2013Date of Patent: February 3, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Naoya Tokiwa, Yasushi Nagadomi
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Patent number: 8885417Abstract: In writing, a first write operation to a first memory cell is executed; and a second write operation for providing a first threshold-voltage distribution to a second memory cell adjacent to the first one, is executed. The first threshold voltage distribution is a lowest threshold-voltage distribution among the positive threshold voltage distributions. It is verified whether a desired threshold voltage distribution has been obtained in the first memory cell or not (first write verify operation), moreover, it is verified whether a first threshold voltage distribution or a threshold voltage distribution having a voltage level larger than the first threshold-voltage distribution has been obtained in the second memory cell or not (second write verify operation). A control circuit outputs results of the first write verify operation and the second write verify operation.Type: GrantFiled: October 4, 2013Date of Patent: November 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yasushi Nagadomi, Naoya Tokiwa
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Publication number: 20140331005Abstract: A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.Type: ApplicationFiled: July 18, 2014Publication date: November 6, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yasushi NAGADOMI
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Publication number: 20140289588Abstract: A memory system (10) is disclosed, which comprises a flash-EEPROM nonvolatile memory (11) having a plurality of memory cells that have floating gates and in which data items are electrically erasable and writable, a cache memory (13) that temporarily stores data of the flash-EEPROM nonvolatile memory (11), a control circuit (12, 14) that controls the flash-EEPROM nonvolatile memory (11) and the cache memory (13), and an interface circuit (16) that communicates with a host, in which the control circuit functions to read data from a desired target area to-be-determined of the flash-EEPROM nonvolatile memory and detect an erased area to determine a written area/unwritten area by using as a determination condition whether or not a count number of data “0” of the read data has reached a preset criterion count number.Type: ApplicationFiled: June 4, 2014Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasushi NAGADOMI, Daisaburo Takashima, Kosuke Hatsuda
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Patent number: 8832362Abstract: A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.Type: GrantFiled: October 25, 2013Date of Patent: September 9, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Yasushi Nagadomi
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Patent number: 8732553Abstract: The embodiments include an error correction processing unit and an error correction history recording unit. The error correction processing unit performs an error correction process based on data read from a non-volatile semiconductor memory and a second-step error correction code corresponding to the data. The error correction history recording unit records error correction history indicating whether first error correction is successful through the first error correction process, in association with unit data. When error correction history of target unit data to be read indicates that correction is not successful, the second error correction process is executed without executing the first error correction process.Type: GrantFiled: September 21, 2011Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yasushi Nagadomi, Daisaburo Takashima
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Publication number: 20140098609Abstract: According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality of bit lines. The row decoder applies a voltage to the first and second select transistors. The controller detects a defect of the bit lines based on data read from the memory cells.Type: ApplicationFiled: June 7, 2013Publication date: April 10, 2014Inventors: Naoya TOKIWA, Yasushi NAGADOMI