Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.

Abstract: A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.

Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.

Abstract: In writing, a first write operation to a first memory cell is executed; and a second write operation for providing a first threshold-voltage distribution to a second memory cell adjacent to the first one, is executed. The first threshold voltage distribution is a lowest threshold-voltage distribution among the positive threshold voltage distributions. It is verified whether a desired threshold voltage distribution has been obtained in the first memory cell or not (first write verify operation), moreover, it is verified whether a first threshold voltage distribution or a threshold voltage distribution having a voltage level larger than the first threshold-voltage distribution has been obtained in the second memory cell or not (second write verify operation). A control circuit outputs results of the first write verify operation and the second write verify operation.

Abstract: A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.

Abstract: In writing, a first write operation to a first memory cell is executed; and a second write operation for providing a first threshold-voltage distribution to a second memory cell adjacent to the first one, is executed. The first threshold voltage distribution is a lowest threshold-voltage distribution among the positive threshold voltage distributions. It is verified whether a desired threshold voltage distribution has been obtained in the first memory cell or not (first write verify operation), moreover, it is verified whether a first threshold voltage distribution or a threshold voltage distribution having a voltage level larger than the first threshold-voltage distribution has been obtained in the second memory cell or not (second write verify operation). A control circuit outputs results of the first write verify operation and the second write verify operation.

Abstract: A non-volatile semiconductor memory device according to an aspect includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory cells, and stores initial setting data in each of a plurality of storage areas. The control circuit reads the initial setting data from the storage areas. The control circuit is configured to read, when it detects an error in the initial setting data read from one of the storage areas, initial setting data from another storage area.

Abstract: A memory system includes a non-volatile memory constituted by blocks each of which is an erase unit constituted by pages each of which is a write/read unit constituted by memory cells; a random access memory temporarily storing data which is written in or read from the non-volatile memory; and a controller controlling the non-volatile memory and the random access memory, wherein the non-volatile memory includes a main memory area in which the block is divided into first management units respectively specified by logical addresses and a cache area in which the block is divided into second management units respectively specified by logical addresses, a data capacity of one of the second management units is smaller than that of one of the first management units, and the controller changes number of the blocks in the main memory area and number of the blocks in the cache area in the non-volatile memory.

Abstract: To provide a memory system that can store data smaller than a block size and data larger than the block size without deteriorating writing efficiency, and can dynamically change a parallelism according to the data.

Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.

Abstract: A non-volatile semiconductor memory device includes a plurality of memory strings, a plurality of memory blocks, a plurality of source-lines, and a control circuit. Each of the memory strings includes a plurality of stacked memory transistors. Each of the memory blocks includes the memory strings. Each of the source-lines are connected to the respective memory strings. The control circuit is configured to output signals to a switch circuit depending on the types of operations for the memory transistors. The switch circuit is capable of connecting the plurality of source-lines electrically and commonly depending on the signals.

Abstract: This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.

Abstract: In writing, a first write operation to a first memory cell is executed; and a second write operation for providing a first threshold-voltage distribution to a second memory cell adjacent to the first one, is executed. The first threshold voltage distribution is a lowest threshold-voltage distribution among the positive threshold voltage distributions. It is verified whether a desired threshold voltage distribution has been obtained in the first memory cell or not (first write verify operation), moreover, it is verified whether a first threshold voltage distribution or a threshold voltage distribution having a voltage level larger than the first threshold-voltage distribution has been obtained in the second memory cell or not (second write verify operation). A control circuit outputs results of the first write verify operation and the second write verify operation.

Abstract: To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used. The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.

Abstract: The embodiments include an error correction processing unit and an error correction history recording unit. The error correction processing unit performs an error correction process based on data read from a non-volatile semiconductor memory and a second-step error correction code corresponding to the data. The error correction history recording unit records error correction history indicating whether first error correction is successful through the first error correction process, in association with unit data. When error correction history of target unit data to be read indicates that correction is not successful, the second error correction process is executed without executing the first error correction process.

Abstract: To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used. The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.

Abstract: This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.

Abstract: A memory system includes a nonvolatile memory, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that performs communication with a host according to an aspect of the preset invention, wherein the control circuit includes a reading unit that outputs a read enable signal to the nonvolatile memory to read data; a delay unit that delays a signal obtained by returning the read enable signal and outputs the signal as a clock, and a latch unit that latches and outputs the data read from the nonvolatile memory by using the clock output from the delay unit.

Abstract: This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.

Abstract: A memory system includes a nonvolatile memory, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that performs communication with a host according to an aspect of the preset invention, wherein the control circuit includes a reading unit that outputs a read enable signal to the nonvolatile memory to read data; a delay unit that delays a signal obtained by returning the read enable signal and outputs the signal as a clock, and a latch unit that latches and outputs the data read from the nonvolatile memory by using the clock output from the delay unit.