Patents by Inventor Yasushi Nagai

Yasushi Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140162623
    Abstract: In this system is provided with a mobile telephone, a server and a vehicle-mounted device with different input/output methods, when an application unit of the mobile telephone is started, control programs and settings suitable for the combination of the vehicle-mounted device, the mobile telephone and the application unit are acquired from the server for an input switching unit, output switching unit, vehicle-internal communication control unit, input control unit and display control unit of the vehicle-mounted device and for an input switching unit, output switching unit, vehicle-internal communication control unit, input control unit, display control unit, input conversion unit and output conversion unit of the mobile telephone, and, after setup and installation, mobile telephone application programs can be remotely controlled by the vehicle-mounted device by running this application unit.
    Type: Application
    Filed: June 21, 2012
    Publication date: June 12, 2014
    Inventors: Yasushi Nagai, Atsushi Shimizu
  • Publication number: 20140038669
    Abstract: In a system in which an in-vehicle apparatus and a smartphone are connected to each other, screen display switching cannot be performed with priorities of all the applications taken into account as respective terminals carry applications. A management block is provided in an in-vehicle apparatus or in a smartphone. The management block holds priority definitions for starting and displaying applications on both terminals. In response to external input to both terminals, the management block selects the application to be started and displayed. The management block identifies the terminal carrying the selected application, and transmits to the identified terminal a request to start the application and to switch display output accordingly.
    Type: Application
    Filed: January 18, 2013
    Publication date: February 6, 2014
    Applicant: Clarion Co., Ltd.
    Inventors: Atsushi Shimizu, Yasushi Nagai, Takashi Matsumoto, Koichi Mitsui, Hiroyoshi Endo, Tatsuaki Osafune
  • Publication number: 20130325478
    Abstract: Dialogue apparatus configured to carry out a dialogue with a driver and including storage, concentration degree measuring and dialogue units. The storage unit maintains a preference database in which a dialogue candidate of content for a dialogue with the driver and a dialogue effect indicating a degree of improving driver's degree of concentration on driving, are associated with each other. The concentration degree measuring unit measures the driver's degree of concentration on driving. The dialogue unit selects a dialogue candidate based on the dialogue effect in the preference database when the degree of concentration measured by the concentration degree measuring unit falls below a predetermined threshold, then carries out a dialogue by the selected dialogue candidate, and based on the degree of concentration before and after carrying out the dialogue, calculates the dialogue effect of the dialogue, and updates the dialogue effect of the preference database.
    Type: Application
    Filed: May 20, 2013
    Publication date: December 5, 2013
    Applicant: Clarion Co., Ltd.
    Inventors: Takashi MATSUMOTO, Yasushi NAGAI, Yo MIYAMOTO, Takaaki ISHII, Yasuki HORIBE, Tomohiro HARADA
  • Publication number: 20130261888
    Abstract: An input/output limitation information storage unit stores input/output limitation information in which limitation processing for limiting operation input to the application and display output from the application is prescribed by associating the limitation processing with the application. A determination unit acquires a vehicle state of a vehicle, and determines the limitation processing to be applied to the operation input to the application and the display output from the application on the basis of the application running on the terminal device, the vehicle state, and the input/output limitation information. The limitation unit performs the limitation processing determined by the determination unit for the operation input detected by the input control unit and transmitted to the communication control unit, and the display output received by the communication control unit and transmitted to the output control unit.
    Type: Application
    Filed: February 11, 2013
    Publication date: October 3, 2013
    Applicant: Clarion Co. Ltd.
    Inventors: YASUSHI NAGAI, Atsushi Shimizu, Takashi Matsumoto, Takayuki Hirota, Takashi Yamaguchi, Yuji Oohara
  • Publication number: 20130080580
    Abstract: In the case of delivering first-edition data, a distribution data amount increases, resulting in increases in lengths of download time and update time. In a data allocation system including a vehicle-mounted device coupled to a server via a network, the server creates from a data group held by the in-vehicle device difference data indicating a difference(s) between object data and analogous data obtained by combining together analogous data blocks similar to the object data, and delivers allocation information of the difference data and analogous data to the in-vehicle device. This in-vehicle device prepares analogous data from its owning data group in accordance with the allocation information of the analogous data received, and rebuilds for installation the object data from the prepared analogous data and received difference data.
    Type: Application
    Filed: July 26, 2012
    Publication date: March 28, 2013
    Applicant: CLARION CO., LTD.
    Inventors: Yasushi Nagai, Atsushi Shimizu
  • Publication number: 20120331186
    Abstract: The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in the peripheral devices according to the contents in the register when the DMA transfer is executed, an interrupt select unit selects one of plural interrupt signals to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations. Based on these operations the state comparator determines whether to start the DMA transfer, and the transfer unit executes data transfer between the peripheral devices.
    Type: Application
    Filed: September 5, 2012
    Publication date: December 27, 2012
    Inventors: Yasushi NAGAI, Hiroshi NAKAGOE, Shigeki TAIRA
  • Patent number: 8275128
    Abstract: This arithmetic logical unit outputs data to be used in checking the final result of an AES unit that encrypts a plain text block into an encrypted text block based on AES operation, and includes an arithmetic unit for computing parity data created based on XOR operation from an encryption key to be used as a key during AES encryption, parity data created based on XOR operation from a plain text block, and an AES operation halfway result output from the AES unit, and outputting a value that is equivalent to parity data created based on XOR operation from the final result of the AES unit.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: September 25, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Nakagoe, Yasushi Nagai
  • Patent number: 8266340
    Abstract: The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in the peripheral devices according to the contents in the register when the DMA transfer is executed, an interrupt select unit selects one of plural interrupt signals to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations. Based on these operations the state comparator determines whether to start the DMA transfer, and the transfer unit executes data transfer between the peripheral devices.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: September 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yasushi Nagai, Hiroshi Nakagoe, Shigeki Taira
  • Publication number: 20120210133
    Abstract: In the configuration performing a data processing by a hardware processing circuit (accelerator), to provide a technology capable of improving a poorness of processing efficiency by multiple accesses to the data, the following solving means are provided. A network data processing accelerator of the present network data processing apparatus comprises processing units corresponding to each processing of an encryption/decryption, a message authentication, and a checksum, and in the data processing including a combination of each processing, accesses for the same data of the memory and the like through a bus I/F unit and the like is collected together into one time, and a pipeline processing is performed using the least common multiple of the data processing unit of each processing.
    Type: Application
    Filed: April 26, 2012
    Publication date: August 16, 2012
    Inventors: Yasushi Nagai, Hiroshi Nakagoe, Shigeki Taira
  • Publication number: 20120191882
    Abstract: The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in the peripheral devices according to the contents in the register when the DMA transfer is executed, an interrupt select unit selects one of plural interrupt signals to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations. Based on these operations the state comparator determines whether to start the DMA transfer, and the transfer unit executes data transfer between the peripheral devices.
    Type: Application
    Filed: April 2, 2012
    Publication date: July 26, 2012
    Inventors: Yasushi NAGAI, Hiroshi Nakagoe, Shigeki Taira
  • Publication number: 20120124571
    Abstract: When a power supply is cut off on updating programs, improper data remains since the power source to be supplied to the vehicle-mounted device is unstable. The check for the improper data and restoration processing are required for a reactivation processing implemented by an update processing unit so that the update is completed correctly, therefore, the user is waited. In contrast, the update processing also implemented by the update processing unit for a time period during which the power source becomes unstable is interrupted, and implemented for the time period during which the power source voltage is stable. In consequence, the update processing is carried on steadily without making the user wait.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 17, 2012
    Applicant: CLARION CO., LTD.
    Inventors: Yasushi Nagai, Atsushi Shimizu, Hiroyuki Kasuya, Shoichi Akutsu, Shinji Kawamura, Yoshitaka Sumitomo
  • Patent number: 8181024
    Abstract: In the configuration performing a data processing by a hardware processing circuit (accelerator), to provide a technology capable of improving a poorness of processing efficiency by multiple accesses to the data, the following solving means are provided. A network data processing accelerator of the present network data processing apparatus comprises processing units corresponding to each processing of an encryption/decryption, a message authentication, and a checksum, and in the data processing including a combination of each processing, accesses for the same data of the memory and the like through a bus I/F unit and the like is collected together into one time, and a pipeline processing is performed using the least common multiple of the data processing unit of each processing.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: May 15, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yasushi Nagai, Hiroshi Nakagoe, Shigeki Taira
  • Patent number: 8176221
    Abstract: A DMA controller achieving real-time control of a DMA transfer relating to periodically operated peripheral devices at a low cost and with low power consumption.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: May 8, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yasushi Nagai, Hiroshi Nakagoe, Shigeki Taira
  • Publication number: 20110209703
    Abstract: An artificial ventilation apparatus includes: a connecting portion which is connected to a respiratory system of a patient; an inspiratory circuit which is a flow path for flowing a gas from a ventilator to the connecting portion; an expiratory circuit which is a flow path for guiding a gas exhausted from the connecting portion to an exhaust portion of the ventilator; an expiratory valve which blocks a flow of a gas from the exhaust portion toward the connecting portion; a carbon dioxide concentration sensor which is disposed in a circuit that is provided at a downstream side of the expiratory valve and which detects a carbon dioxide concentration; and an alarm outputting unit which outputs an alarm based on an output of the carbon dioxide concentration sensor.
    Type: Application
    Filed: February 26, 2011
    Publication date: September 1, 2011
    Applicant: NIHON KOHDEN CORPORATION
    Inventors: Yutaka USUDA, Naofumi KOBAYASHI, Shinji YAMAMORI, Yasushi NAGAI
  • Publication number: 20110041135
    Abstract: A data processing method has a device control thread for each peripheral device capable of an independent operation, a CPU processing thread for each data processing that is performed by a CPU, a control thread equipped with a processing part for constructing an application. The control thread checks an output from the thread related with each processing part, performs with a higher priority from the processing part in which output data of the preprocessing part as a configuration of the application exists and that is near termination, and instructs execution of the each device control thread and the CPU processing thread, and data input/output. Each of device control thread and CPU processing thread processes the data according to the instructions, and sends a processing result and a notification to the control thread.
    Type: Application
    Filed: June 29, 2010
    Publication date: February 17, 2011
    Applicant: CLARION CO., LTD.
    Inventor: Yasushi NAGAI
  • Patent number: 7853733
    Abstract: An operational circuit for performing an operation of an arbitrary number of input data pieces by using a DMA transfer according to a descriptor control and output results. The arbitrary number of input data pieces are divided into a plurality of pieces to perform an operation processing without performing the operation of the arbitrary number of input data pieces at a time. The operational circuit once stores an intermediate result for each of the divided operations in an external storage device, performs an operation processing read with an intermediate result in the next operation processing, and obtains a final result by repeating these operation processings. The operation is performed at a cyclic unit of processing corresponding to the number of address registers provided in the operational circuit.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: December 14, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Nakagoe, Yasushi Nagai
  • Publication number: 20100257288
    Abstract: A DMA controller achieving real-time control of a DMA transfer relating to periodically operated peripheral devices at a low cost and with low power consumption.
    Type: Application
    Filed: March 21, 2008
    Publication date: October 7, 2010
    Inventors: Yasushi Nagai, Hiroshi Nakagoe, Shigeki Taira
  • Publication number: 20100241771
    Abstract: A peripheral circuit with a host load adjusting function which is capable of readily carrying out control so that the amounts of data processed by the peripheral circuit and a host CPU are balanced by limiting interrupts made by the peripheral circuit, usage of a memory bus bandwidth, and a processing throughput of data. A typical embodiment of the present invention has an adjustment limitation setting unit setting a minimum value of an interval of interrupt requests generated by the peripheral circuit with the host load adjusting function, and a cycle counter counting generation timing of the interrupt requests, and compares a value of the cycle counter with the interval set in the adjustment limitation setting unit, thereby suppressing the interrupt requests generated at an interval shorter than the set interval.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 23, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Yasushi Nagai, Hiroshi Nakagoe, Shigeki Taira
  • Publication number: 20090265443
    Abstract: This network apparatus includes a confirmation unit for confirming an appliance connected to a network in a certain area at predetermined time intervals, a transfer unit for transferring a content retained in the appliance from the appliance connected to the network to a storage apparatus outside of the area, a setting unit for setting a virtual device of the appliance when the confirmation unit detects that the appliance has been disconnected from the network, and a distribution unit for distributing, when an acquisition request of the content is issued to the appliance disconnected from the network, the content read from the storage to a sending source of the acquisition request with the virtual device as the transmission source of the content.
    Type: Application
    Filed: June 16, 2008
    Publication date: October 22, 2009
    Inventors: Hirotaka Moribe, Shoji Kodama, Yasushi Nagai
  • Publication number: 20090222798
    Abstract: A mobile device includes a memory for storing therein a subroutine management table to manage kinds of existing codes out of native code, first code and second code for a plurality of subroutines contained in content, a virtual machine, a precompile circuit for producing second code from first code and a subroutine management circuit for changing over processing in accordance with the kind of existing code for subroutine called up during execution of content. The subroutine management circuit judges kind of existing code with reference to the subroutine management table when the processing is changed over.
    Type: Application
    Filed: December 11, 2008
    Publication date: September 3, 2009
    Inventors: Shinya IGUCHI, Takatoshi Kato, Masaya Umemura, Nobuaki Kohinata, Yasushi Nagai, Hiroshi Nakagoe, Keitaro Okasaki, Hirotaka Moribe, Takeshi Asahi