Abstract: An adaptive equalizer includes: an adaptive filter; and a control unit. The adaptive filter performs an adaptive equalization processing for an input signal modulated by a modulation method that produces a modulation signal with constant amplitude characteristics so as to make an amplitude of an equalized output signal constant. The control unit controls stop and execution of the adaptive equalization processing of the adaptive filter in accordance with characteristics of at least one of the input signal and the output signal.

Abstract: An adaptive equalizer includes an adaptive filter and a control unit. The adaptive filter performs an adaptive equalization processing for an input signal so as to make an amplitude of an equalized output signal constant, the input signal being modulated by a modulation system that produces a modulation signal with constant amplitude characteristics. The control unit gradually changes equalization ability of the adaptive equalization processing of the adaptive filter in accordance with characteristics of the input signal.

Abstract: A radio receiver includes a frequency converter, an oscillation circuit, an A/D converter, and a digital demodulator. The A/D converter digitally samples the intermediate frequency signal by using one of an oscillating frequency, a multiplying frequency, and a dividing frequency of the clock signal as a sampling frequency. The digital demodulator performs a digital demodulation processing by using the intermediate frequency signal digitally sampled and by using the one of the oscillating frequency, the multiplying frequency, and the dividing frequency of the clock signal as an operating frequency. The oscillating frequency is within a predetermined range. The predetermined range is at least one of equal to or more than 37.1 MHz and less than or equal to 37.9 MHz, equal to or more than 54.1 MHz and less than or equal to 64.8 MHz, and equal to or more than 74.2 MHz and less than or equal to 75.8 MHz.

Abstract: A sampling apparatus for converting first data, sampled at a first sampling rate, into second data, sampled at a second sampling rate. A FIFO storing the first data based on a write control signal and outputs the second data read out based on a read control signal indicating whether the second data is to be read out during the next time interval. The apparatus further includes a frequency detection unit for measuring the first clock signal during the current time interval to generate the value of the first current clock frequency, generating the value of a current predicted clock frequency from the value of the first current clock frequency and the value of the directly previously predicted clock frequency and for using the value of the current predicted clock frequency as the directly previously predicted clock frequency during the next time interval.

Abstract: An adaptive equalizer includes an adaptive filter and a control unit. The adaptive filter performs an adaptive equalization processing for an input signal so as to make an amplitude of an equalized output signal constant, the input signal being modulated by a modulation system that produces a modulation signal with constant amplitude characteristics. The control unit gradually changes equalization ability of the adaptive equalization processing of the adaptive filter in accordance with characteristics of the input signal.

Abstract: A radio receiver includes a frequency converter, an oscillation circuit, an A/D converter, and a digital demodulator. The A/D converter digitally samples the intermediate frequency signal by using one of an oscillating frequency, a multiplying frequency, and a dividing frequency of the clock signal as a sampling frequency. The digital demodulator performs a digital demodulation processing by using the intermediate frequency signal digitally sampled and by using the one of the oscillating frequency, the multiplying frequency, and the dividing frequency of the clock signal as an operating frequency. The oscillating frequency is within a predetermined range. The predetermined range is at least one of equal to or more than 37.1 MHz and less than or equal to 37.9 MHz, equal to or more than 54.1 MHz and less than or equal to 64.8 MHz, and equal to or more than 74.2 MHz and less than or equal to 75.8 MHz.

Abstract: An adaptive equalizer according to an embodiment of the present invention includes: an adaptive filter; and a control unit. The adaptive filter performs an adaptive equalization processing for an input signal modulated by a modulation method that produces a demodulated signal with constant amplitude characteristics so as to make an amplitude of an equalized output signal constant. The control unit controls stop and execution of the adaptive equalization processing of the adaptive filter in accordance with characteristics of at least one of the input signal and the output signal.

Abstract: In a video coding apparatus, coding/decoding circuitry provides motion-compensated inter-frame prediction coding on input frames by using reference frames so that the input frames are coded into an intra-frame coded picture, a predictive coded picture or a bi-directionally predictive coded picture and decoding the coded frames to produce reference frames. Decision circuitry determines the magnitude of motion of the input frames relative to the reference frames, determines the interval between successive frames of the predictive coded picture according to the determined magnitude of motion and reorders the input frames according to the determined interval.

Abstract: Disclosed is a sampling rate conversion apparatus for converting first data, sampled at a first sampling rate, into second data, sampled at a second sampling rate, includes a FIFO for storing the first data responsive to a first clock signal and for outputting the first data as second data responsive to the second clock signal. This FIFO stores the first data based on a write control signal indicating whether or not the first data written directly previously is to be updated to the first data, and outputs the second data read out based on a read control signal indicating whether or not the second data as read out is to be read out during the next time interval as well.

Abstract: Video images including a fade transition are encoded using inter-frame prediction. A fade detector is provided to detect a fade transition by way of analyzing incoming images successively applied thereto. The fade detector generates first information indicating if the fade transition is fade-in fade-out, and also predicts fade duration and then generates second information indicating the predicted fade duration. A bit amount adjuster is provided to adjust allocated bit amount during fade using the first and second information. A motion image encoder is provided to encode the incoming images using the number of bits which has been determined by the bit amount adjuster.

Abstract: In a motion vector estimating apparatus, a current picture storage unit stores image data of a current picture, and a reference-picture storage unit stores image data of a reference picture. A search window determining unit determines estimation history from previously estimated motion vectors, and determines a search window based on the estimation history. At least one of a shape, size and position of the search window is determined based on the estimation history. The search window is composed of rectangular reference regions. A block matching circuit for performing a block matching process to a current block and each of reference blocks of the search window to determine a motion vector. The search window may be limited in units of pixels, or a load of the apparatus, a power supply voltage or a temperature of the block matching circuit.

Abstract: In a motion vector estimating apparatus, a current picture storage unit stores image data of a current picture, and a reference picture storage unit stores image data of a reference picture. A search window determining unit determines estimation history from previously estimated motion vectors, and determines a search window based on the estimation history. At least one of a shape, size and position of the search window is determined based on the estimation history. The search window is composed of rectangular reference regions. A block matching circuit for performing a block matching process to a current block and each of reference blocks of the search window to determine a motion vector. The search window may be limited in units of pixels, or a load of the apparatus, a power supply voltage or a temperature of the block matching circuit.

Abstract: Video-inputting portion 3, video-outputting portion 8, motion-estimating portion 4, pixel-level-arithmetic portion 5, variable-length-encoding portion 6, and code-outputting portion 7 are coupled with frame memory 10 through buffer and frame memory controlling portion 9 and controlling processor 1 through host interface portion 2. Frame memory 10 is accessed by video-inputting portion 3, video-outputting portion 8, motion-estimating portion 4, pixel-level-arithmetic portion 5, variable-length-encoding portion 6, and code-outputting portion 7 in time sharing manner. Controlling of video-inputting portion 3, video-outputting portion 8, motion-estimating portion 4, pixel-level-arithmetic portion 5, variable-length-encoding portion 6, and code-outputting portion 7 is centralized in controlling processor 1. Portions in dotted frame 20 are integrated in one LSI chip.

Abstract: A moving picture coding and decoding circuit which can cope with a plurality of algorithms to reduce the number of components and facilitate extension. A picture to be coded is inputted to a motion detection/prediction section, which outputs a predictive difference signal and a predictive signal. DCT processing and quantization are performed for the predictive difference signal by a conversion coding and decoding section, from which a conversion coefficient signal is outputted to an interface bus. The conversion coding and decoding section also executes dequantization and inverse DCT processing of the conversion coefficient, adds the predictive signal to the conversion coefficient and outputs a result of the picture coding to an image data bus. A programmable architecture as in a digital signal processor is applied to the conversion coding and decoding section.

Abstract: A pipelined data processing system has an instruction set containing a stall instruction, and includes a plurality of stages and a pipeline controller for controlling execution and stall of a pipeline operation. The pipeline controller is configured to put the stages into a "frozen" condition on the basis of a stall signal generated by execution of the stall instruction, and to return the stages from the "frozen" condition to a "run" condition on the basis of an output pulse generated by a timer designated by an operand part of the stall instruction.

Abstract: A data processing system for a picture coding, includes a data memory for storing a discrete cosine transform (DCT) coefficient data successively transferred one after another, a flipflop set prior to the successive transfer of the DCT coefficient data, and a non-zero detector for detecting a non-zero data when the DCT coefficient data is successively transferred. When the non-zero data is detected, the non-zero detector resets the flipflop. When the successive transfer of the DCT coefficient data has been completed, an entropy coding central processing unit (CPU) discriminates on the basis of the condition of the flipflop whether or not all of the data stored in the data memory is zero, so that if the condition of the flipflop indicates that all of the data stored in the data memory is zero, the entropy coding CPU does not read the data memory.

Abstract: An address generating circuit having a two-dimensional coding table which has respective coded words corresponding to a combination of x and y where the value of event A is determined as x and the value of event B as y (x and y are positive integers) between two events A and B, and stores the coded words in an address corresponding to each combination of x and y; coincidence detectors which input the values x and y of the events A and B and detect whether these values coincide with the integer of 1 to S (S is the maximum number among the integers satisfying S+log.sub.2 S<P and P is a positive integer); comparators which examine whether the inputted y satisfies x+log.sub.2 y.ltoreq.P for each integral number of x, and examine whether the inputted x satisfies y+log.sub.2 x.ltoreq.

Abstract: A variable length code decoding circuit includes a decoding table storing data, which has an upper field selectively indicative of a meaning of the code and an address for next access, selected depending upon a state transition upon decoding the variable bit length code per n bits (n is an integer greater than or equal to 2), an intermediate field indicative of a shifting magnitude of the shift register upon completion of decoding, and a lower field indicative of a state of code decoding. The bit sequence of the variable bit length code in a shift register is shifted in a magnitude corresponding to a shifting magnitude indicated in the intermediate field when data indicative of the code decoding state in the lower field of the data read out from the decoding table storage means indicates completion of decoding and corresponding to n bits when the data indicative of the code decoding state in the lower field indicates continuation of decoding.

Abstract: A nesting management mechanism for use in a loop controlling system, comprises a program counter coupled to a program counter bus and incremented each time one instruction is executed, and a loop counter coupled with the program counter bus and set with the number of loops to be executed when a loop execution is executed. The loop counter is decremented each time one loop is completed. A loop start address register is coupled to the program counter bus and set with a loop start address when the loop execution is executed, and a loop end address register is coupled to the program counter bus and set with a loop end address when the loop execution is executed. First, second and third independent hardware stacks of a first-in last-out type are provided for the loop counter, the loop start address register, and the loop end address register, respectively, so as to save respective contents of the loop counter, the loop start address register, and the loop end address register at the time of a loop nesting.

Abstract: A data processor which includes at least a central processing unit adapted to execute virtual memory management. The central processing unit internally includes a translation lookaside buffer (TLB) for translating a given virtual address into a corresponding real address. The TLB also generates a distinction signal indicating whether the translated real address designates a main memory or an external input/output device. In response to the distinction signal, a control signal generator outputs a set of input/output control signals for the access of the type designated by the distinction signal.