Abstract: In a vector calculation unit (31), a multiplication and an addition result register (50 and 53) are connected to a pipeline multiplier (14) and a pipeline adder (15), respectively. A multiplication and an addition result bus (52 and 55) are connected to the multiplication and the addition result registers, respectively. A selector (S1) connects one of an input bus (11) and the multiplication and the addition result buses to the first operand register to which a first multiplication and a first addition operand bus (44 and 45') are connected. A selector (S2) connects one of another input bus (12) and the multiplication and the addition result buses to the second operand register to which second multiplication and second addition operand buses (48 and 49) are connected. A selector (S3) connects one of the first multiplication operand, the multiplication result, and the addition result buses to an input of the multiplier.

Abstract: A processor capable of processing a variable word length instruction has a program counter controlled to indicate the head of an instruction by the value of the program counter. There are provided an adder for summing the length of decoded portions in the variable word length instruction in accordance with the progress of the instruction decoding, and another adder for adding the length of the decoded instruction portions to the program counter so as to update the program counter. Further, there is provided a circuit for calculating an operand effective address by using the value of the program counter in the course of the variable word length instruction decoding. Thus, the updating of the program counter and the generation of the effective address are concurrently executed.

Abstract: A data processing apparatus has a plurality of execution status and is adapted to control in accordance with the respective execution conditions the allowance of the execution of an instruction requiring the reference to the internal resource. The processing apparatus also comprises a register for holding the execution status, and another register for holding information controlling the reference to the internal resource. A comparator responds to the contents of the first and second registers to output a signal indicating whether the reference is allowed or not. The output signal and a strobe signal are fed to a gate, which then controls an actual reference to the internal resource.

Abstract: An instruction code access control system used in an instruction code prefetched computer system includes at least an instruction buffer for accumulating prefetched instruction codes, and a data path switch for selectively coupling the instruction buffer to a data path through which an instruction code and an operand data are selectively transferred. The system also comprises a fetch counter for counting the number of the instruction codes accumulated in the instruction buffer from the time a discontinuous program control is carried out. There is provided a counter detector for comparing the value of the fetch counter with a predetermined value. An arbiter is provided for determining, on the basis of the output of the counter detector, a priority between an instruction memory access for instruction code prefetching and an operand access caused as the result of an instruction execution. The arbiter operates to control the data path switch in accordance with the result of the determination.

Abstract: An associative type cache controller includes a plurality of directory banks each holding an address tag of a cache block, each of the directory banks having a comparison circuit for comparing the content of the directory bank with a tag portion of a current reference address. The cache controller comprises a register for holding the association unit number, and a replacement block determining unit for indicating, in accordance with the content of the association unit number holding register, the directory bank including the cache block to be replaced at the time of cache replacement, so that the replacement directory banks are limited in accordance with the designated association unit number. Thus, the association unit number of a related cache memory can be changeably designated.