Abstract: The present invention is to provide an automatic IP core generation system that can reduce the loads on both an IP core vendor and a user. The present invention provides an automatic IP core generation system that generates an IP core in accordance with parameter information input from a user. The automatic IP core generation system includes: a parameter acquisition unit that acquires the parameter information; a meta IP core information storage unit that stores a meta IP core model as a model for generating various IP cores; a component library information storage unit that stores a component to be used in the IP core and the meta IP core model; an IP core generation unit that generates a package containing the IP core in accordance with the parameter information; and a package output unit that outputs the package.

Abstract: The present invention is to provide an automatic IP core generation system that can reduce the loads on both an IP core vendor and a user. The present invention provides an automatic IP core generation system that generates an IP core in accordance with parameter information input from a user. The automatic IP core generation system includes: a parameter acquisition unit that acquires the parameter information; a meta IP core information storage unit that stores a meta IP core model as a model for generating various IP cores; a component library information storage unit that stores a component to be used in the IP core and the meta IP core model; an IP core generation unit that generates a package containing the IP core in accordance with the parameter information; and a package output unit that outputs the package.

Abstract: A disclosed semiconductor design support apparatus reads circuit description information and generates information required for delay adjustment. The semiconductor design support apparatus includes a logic simulation unit configured to perform logic simulation based on the circuit description information and output logic simulation result information; a latency information acquiring unit configured to acquire, from the logic simulation result information, latency information relating to signals at a signal junction, the signals being output from multiple blocks; an adjustment latency calculating unit configured to calculate, from the latency information, adjustment latency information required for the delay adjustment; and an adjustment delay information generating unit configured to generate, from the adjustment latency information, adjustment delay information required for the delay adjustment.

Abstract: A program development support system includes a reader, a designator, and a comparator. The reader is configured to read first and second programs executing operations which are expected to be identical to each other. The designator is configured to designate a variant pair of a first variant included in the first program and a second variant included in the second program. The first and second variants are expected to be identical to each other. The comparator is configured to compare values between the first and second variants when the first and second programs are executed.

Abstract: A disclosed semiconductor design support apparatus reads circuit description information and generates information required for delay adjustment. The semiconductor design support apparatus includes a logic simulation unit configured to perform logic simulation based on the circuit description information and output logic simulation result information; a latency information acquiring unit configured to acquire, from the logic simulation result information, latency information relating to signals at a signal junction, the signals being output from multiple blocks; an adjustment latency calculating unit configured to calculate, from the latency information, adjustment latency information required for the delay adjustment; and an adjustment delay information generating unit configured to generate, from the adjustment latency information, adjustment delay information required for the delay adjustment.

Abstract: A semiconductor design support device for designing a semiconductor integrated circuit includes a behavioral description, an RTL description, and a latency analyzer. The behavioral description describes an algorithm of processing performed by hardware in a motion level. The RTL description is generated by reading the behavioral description and recognizes a concept including register and clock synchronism peculiar to the hardware. The latency analyzer analyzes a result of a logic simulation performed on the RTL description to calculate a latency in each block representing an operation in a predetermined unit in the behavioral description.

Abstract: A semiconductor design support device for designing a semiconductor integrated circuit includes a behavioral description, an RTL description, and a latency analyzer. The behavioral description describes an algorithm of processing performed by hardware in a motion level. The RTL description is generated by reading the behavioral description and recognizes a concept including register and clock synchronism peculiar to the hardware. The latency analyzer analyzes a result of a logic simulation performed on the RTL description to calculate a latency in each block representing an operation in a predetermined unit in the behavioral description.

Abstract: A method for performing scan test on a semiconductor integrated circuit including at least two blocks to be tested. The method includes isolating each of the at least two blocks to be tested exclusively from further blocks; and supplying a plurality of scan clocks having different phases each to each of the at least two blocks. In addition, a semiconductor integrated circuit includes at least two blocks to be tested, an Core Wrapper Architecture isolation unit for isolating each of the at least two blocks to be tested exclusively from further blocks, and an input terminal for inputting a plurality of scan clocks each to each of the at least two blocks, in which a Wrapper register included in the Core Wrapper Architecture is configured to be supplied selectively with one of a scan clock and a system clock for the blocks.

Abstract: A computer readable medium includes computer executable code stored thereon, the code for estimating power consumption of an integrated circuit, comprising code for simulating logic of basic and mega cells of the integrated circuit, code for estimating a current consumed by the mega cells by obtaining logic states for each mega cell, determining an average operation frequency for each logic state, and determining an alternating current component and a direct current component for each logic state to calculate said current consumed by the mega cells for estimating a first value of electric power consumed by said mega cells based on said logic simulations and pre-established power consumption data, code for estimating a current consumed by the basic cells for estimating a second value of electric power consumed by said basic cells based on said logic simulations and pre-established power consumption data and code for combining said first and second values to obtain the power consumption of the integrated circui

Abstract: A logic circuit simulation apparatus used in designing a logic IC (integrated circuit) is provided. The logic circuit simulation apparatus includes a power control signal specifying unit which creates power control signal information for specifying statuses of a plurality of power control signals, a logic circuit simulation control information generation unit which reads the power control signal information and related circuit connection information and generates a logic circuit simulation control information based on the power control signal information and the circuit connection information, and a logic circuit simulation unit which fixes with high impedance each input of a circuit block to which power is not supplied in accordance with the logic circuit simulation control information, simulating the logic circuit.

Abstract: A program development support system includes a reader, a designator, and a comparator. The reader is configured to read first and second programs executing operations which are expected to be identical to each other. The designator is configured to designate a variant pair of a first variant included in the first program and a second variant included in the second program. The first and second variants are expected to be identical to each other. The comparator is configured to compare values between the first and second variants when the first and second programs are executed.

Abstract: A logic circuit simulation apparatus used in designing a logic IC (integrated circuit) is provided. The logic circuit simulation apparatus includes a power control signal specifying unit which creates power control signal information for specifying statuses of a plurality of power control signals, a logic circuit simulation control information generation unit which reads the power control signal information and related circuit connection information and generates a logic circuit simulation control information based on the power control signal information and the circuit connection information, and a logic circuit simulation unit which fixes with high impedance each input of a circuit block to which power is not supplied in accordance with the logic circuit simulation control information, simulating the logic circuit.

Abstract: An analysis part analyzes a description of a logic design; an extraction part extracts a part of the description of the logic design having a fan-out number beyond a predetermined value, based on the analysis; an insertion part inserts a buffer for clock tree synthesis for performing an adjustment on the part extracted by said extracting part, the adjustment being performed at a time of subsequent layout process; and a logic synthesis part performs logic synthesis on the description of the logic design obtained after the insertion performed by said inserting part.

Abstract: Disclosed is a method for performing scan test on a semiconductor integrated circuit including at least two blocks to be tested each capable of performing active functions. The method includes at least the steps of isolating each of the at least two blocks to be tested exclusively from further blocks; and supplying a plurality of scan clocks each to each of the at least two blocks, in which the plurality of scan clocks each have the phase different from each other.

Abstract: An analysis part analyzes a description of logic design; an extraction part extracts a part of the description of logic design having the fan-out number beyond a predetermined value, based on the analysis; an insertion part inserts a buffer for clock tree synthesis for performing an adjustment on the part extracted by said extracting part, the adjustment being performed at a time of subsequent layout process; and a logic synthesis part 50 performs logic synthesis on the description of logic deign obtained after the insertion performed by said inserting part.

Abstract: Operation cycles to be subjected to an IDDQ test are selected from among operation cycles defined by a test pattern for a functional test of a CMOS integrated circuit so that a sufficient and necessary number of operation cycles are accurately and rapidly selected. A combination of sets of m-bit data are selected so that the combination includes sets of m-bit data each bit of which is changed from one of the values "0" and "1" to the other at least once. The operation cycles corresponding to the sets of m-bit data included in the combination are rendered to be the IDDQ test cycles to be subjected to the IDDQ test.

Abstract: A method and an apparatus are provided for estimating electric power consumption of integrated circuits from the values of power consumption by basic cells and mega cells. Power consumption is estimated based on logic simulation results and power consumption data for each logic state at each of input and output terminal of each basic cell and each mega cell.

Abstract: An LSI design aiding apparatus includes an operating-part net list generation unit for generating an operating-part net list from a net list of a logical circuit, the net list including information relating to a plurality of logical elements in the logical circuit and information relating to connections involving the plurality of logical elements, and the operating-part net list describing an operating part of the logical circuit which is in operation during a predetermined logical operation, so as to perform an estimation of current consumption, synthesis of the logical circuit adapted for low power consumption, and generation of layout data adapted for low power consumption.

Abstract: A logic circuit simulation apparatus used in designing a logic IC (integrated circuit) is provided. The logic circuit simulation apparatus includes a power control signal specifying unit which creates power control signal information for specifying statuses of a plurality of power control signals, a logic circuit simulation control information generation unit which reads the power control signal information and related circuit connection information and generates a logic circuit simulation control information based on the power control signal information and the circuit connection information, and a logic circuit simulation unit which fixes with high impedance each input of a circuit block to which power is not supplied in accordance with the logic circuit simulation control information, simulating the logic circuit.