SEMICONDUCTOR DESIGN SUPPORT APPARATUS
A disclosed semiconductor design support apparatus reads circuit description information and generates information required for delay adjustment. The semiconductor design support apparatus includes a logic simulation unit configured to perform logic simulation based on the circuit description information and output logic simulation result information; a latency information acquiring unit configured to acquire, from the logic simulation result information, latency information relating to signals at a signal junction, the signals being output from multiple blocks; an adjustment latency calculating unit configured to calculate, from the latency information, adjustment latency information required for the delay adjustment; and an adjustment delay information generating unit configured to generate, from the adjustment latency information, adjustment delay information required for the delay adjustment.
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This patent application is based upon and claims the benefit of priority of Japanese Patent Application No. 2010-044598 filed on Mar. 1, 2010 the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention is generally directed to electronic design technologies for semiconductor products.
2. Description of the Related Art
For designing pipelined circuits, it may be required to design latency (the amount of delay) of each block to be the same among multiple blocks. The term “latency” here refers to a clock cycle number from when data reach the input of a block to when the data are transmitted to the output of the block.
Adjustment of such latency is explained with reference to
With such pipelined circuits, in some cases, the data arrival time (clock cycle time) needs to be the same between inputs CIN0 and CIN1 of Block C in
In such conditions, the data arrival times at the inputs CIN0 and CIN1 of Block C are conventionally set to be the same in the following manner.
First, the data arrival times at the inputs CIN0 and CIN1 of Block C are visually checked based on logic simulation results, and the difference between the data arrival times is calculated manually.
Next, if there is a difference in the data arrival times, a register (flip-flop) or registers for latency adjustment are manually inserted into circuit data.
Thus in the case of calculating the difference in the data arrival times and inserting a register/registers manually, if there are many data junctions, a point or points at which the data arrival times are not the same may fail to be noticed, or the difference in the data arrival times may be incorrectly calculated. As a result, the design efficiency decreases.
In order to solve such problems, Patent Document 1 discloses a technique for, by high-level synthesis, adjusting latency among multiple threads which operate concurrently.
- [Patent Document 1] Japanese Patent No. 3763700
However, because of being based on high-level synthesis, the technique disclosed in Patent Document 1 is not applicable for adjusting latency between a block designed by high-level synthesis and a block designed by existing design technology which is not high-level synthesis. Also, the disclosed technique cannot be applied to a circuit composed only of blocks designed by existing design technology which is not high-level design technology.
SUMMARY OF THE INVENTIONAccordingly, embodiments of the present invention may provide a novel and useful design apparatus solving one or more of the problems discussed above.
More specifically, the embodiments of the present invention may provide a semiconductor design support apparatus capable of applying latency adjustment also to blocks designed by existing design technology which is not high-level design technology.
One aspect of the present invention may be to provide a semiconductor design support apparatus that reads circuit description information and generates information required for delay adjustment. The semiconductor design support apparatus includes a logic simulation unit configured to perform logic simulation based on the circuit description information and output logic simulation result information; a latency information acquiring unit configured to acquire, from the logic simulation result information, latency information relating to signals at a signal junction, the signals being output from multiple blocks; an adjustment latency calculating unit configured to calculate, from the latency information, adjustment latency information required for the delay adjustment; and an adjustment delay information generating unit configured to generate, from the adjustment latency information, adjustment delay information required for the delay adjustment.
Another aspect of the present invention is a semiconductor design support control method applied to a semiconductor design support apparatus that reads circuit description information and generates information required for delay adjustment. The semiconductor design support control method includes a logic simulation step of performing logic simulation based on the circuit description information and outputting logic simulation result information; a latency information acquiring step of acquiring, from the logic simulation result information, latency information relating to signals at a signal junction, the signals being output from multiple blocks; an adjustment latency calculating step of calculating, from the latency information, adjustment latency information required for the delay adjustment; and an adjustment delay information generating step of generating, from the adjustment latency information, adjustment delay information required for the delay adjustment.
Yet another aspect of the present invention is a computer-readable storage medium storing a semiconductor design support control program for causing a computer to execute a process. The computer constitutes a semiconductor design support apparatus that reads circuit description information and generates information required for delay adjustment. The process includes a logic simulation step of performing logic simulation based on the circuit description information and outputting logic simulation result information; a latency information acquiring step of acquiring, from the logic simulation result information, latency information relating to signals at a signal junction, the signals being output from multiple blocks; an adjustment latency calculating step of calculating, from the latency information, adjustment latency information required for the delay adjustment; and an adjustment delay information generating step of generating, from the adjustment latency information, adjustment delay information required for the delay adjustment.
Additional objects and advantages of the embodiments will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
A description is given below, with reference to the
In
The logic simulation unit 31 inputs the circuit description information 21 from the storage area 2, then performs logic simulation and outputs the logic simulation result information 22 to the storage area 2. Specific examples of the circuit description information 21 include circuit descriptions using hardware description languages, such as Verilog HDL and SystemC. In the present embodiment, an RTL (Register Transfer Level) description in Verilog HDL is used as a specific example of the circuit description information 21.
The logic simulation result information 22 includes information of signal names and signal values associated with times (clock cycle times). Note that instead of explicitly outputting the logic simulation result information 22 to the storage area 2, the succeeding latency information acquiring unit 32 may acquire necessary logic simulation result information from the logic simulation unit 31 using an API (Application Programming Interface) installed in the logic simulation unit 31. A specific API is, for example, “VPI (Verilog Procedural Interface)”.
The logic simulation unit 31 usually applies a test pattern for verifying functions of the circuit to an external input of the circuit description. In the case of an RTL description, the external input is an externally input valid signal, and the logic simulation unit 31 performs logic simulation by applying a logical value “0” or “1” to the valid signal.
In the above test pattern, a valid signal inside the circuit is initialized to the logical value “0” at the start of the logic simulation, and the logical value “1” is applied to the externally input valid signal at a predetermined timing. Assume that, after the logical value “1” is applied to the externally input valid signal, the logical value of the internal valid signal changes to “1” during the logic simulation. In this case, the time of the logical value change indicates the time when data have arrived at the internal signal position. It is therefore possible to know latency from the difference between the arrival time and the time of the application of the logical value “1”.
The valid signals are more specifically explained with reference to
Referring back to
Assume here that the time when the logical value “1” is applied to the external signals valid_a and valid_b is “0”, and that time “1” corresponds to 1 clock cycle. In this case, the logic simulation result information 22 based on the circuit description information 21 shown in
Referring back to
Referring back to
The following procedures can be used to cause the signal arrival times of valid_c0 and valid_c1 to be the same based on the circuit description information 21 of
The adjustment delay information generating unit 34 generates a circuit description in which, as shown in
In
According to the above first embodiment, the processing is started with the circuit description information 21 that is an RTL description or the like; however, in the second embodiment, the processing is started with the circuit description information 201 which is, for example, a high-level circuit description in SystemC or the like.
As preprocessing, FIFOs (First-In First-Out) with a depth of “1” are placed, within the circuit description information 201, at parts requiring latency adjustment. This placement is handled by the user of the semiconductor design support apparatus 1.
Referring back to
Referring back to
In order that latency of each block can be determined at following functional units, the logic simulation unit 302 initializes valid signals inside the circuit to the logical value “0” at the start of the logic simulation, and applies the logical value “1” to externally input valid signals at a predetermined timing. In the case of the circuit description information 202 of
Referring back to
Assume here that the time when the logical value “1” is applied to the external signals valid_a and valid_b is “0”, and that time “1” corresponds to 1 clock cycle. In this case, the logic simulation result information 203 based on the circuit description information 202 shown in
Referring back to
Referring back to
In the case when the logic simulation is performed based on the circuit description information 202 of
Referring back to
If the above described first and second embodiments are applied, for example, to an image forming apparatus, the amount of delay to be added for latency adjustment may become significantly large, possibly corresponding to multiple lines of image data. In this case, delay circuits realized by a RAM (Random Access Memory) may be used instead of registers (flip-flops).
[General Overview]The embodiments explained above offer the following advantages.
(1) Latency is calculated not by conventional visual inspection but using a logic simulator, and therefore accurate latency calculation is performed.
(2) Latency is calculated by not a high-level synthesis apparatus but a logic simulator, and therefore latency calculation can be performed for a circuit description which cannot be input to a high-level synthesis apparatus.
(3) In the case of embedding parts requiring latency adjustment in a circuit description, there is no need to provide a new information medium for specifying the parts requiring latency adjustment.
(4) Since information on the amount of delay required for latency adjustment is generated, latency can be adjusted by performing once again high-level synthesis using the information.
According to the embodiments of the present invention, a unit for calculating a difference in data arrival times is provided to a logic simulator, instead of being provided to such a high-level synthesis apparatus disclosed in Patent Document 1. The present invention is therefore capable of applying latency adjustment also to blocks designed by existing design technology which is not high-level design technology.
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority or inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
Claims
1. A semiconductor design support apparatus that reads circuit description information and generates information required for delay adjustment, the semiconductor design support apparatus comprising:
- a logic simulation unit configured to perform logic simulation based on the circuit description information and output logic simulation result information;
- a latency information acquiring unit configured to acquire, from the logic simulation result information, latency information relating to signals at a signal junction, the signals being output from a plurality of blocks;
- an adjustment latency calculating unit configured to calculate, from the latency information, adjustment latency information required for the delay adjustment; and
- an adjustment delay information generating unit configured to generate, from the adjustment latency information, adjustment delay information required for the delay adjustment.
2. The semiconductor design support apparatus as claimed in claim 1, wherein the logic simulation unit records, in the logic simulation result information, a change in a signal value at each part in a circuit in association with a time of the change.
3. The semiconductor design support apparatus as claimed in claim 1, wherein the latency information acquiring unit acquires, from the logic simulation result information, signal latency of the blocks at the signal junction and outputs the signal latency as the latency information.
4. The semiconductor design support apparatus as claimed in claim 1, wherein the adjustment latency calculating unit calculates, from the latency information, a difference in signal latency of the blocks at the signal junction and outputs the difference as the adjustment latency information.
5. The semiconductor design support apparatus as claimed in claim 1, wherein the adjustment delay information generating unit adds, to a block having small latency, a delay circuit corresponding to a difference in signal latency of the blocks at the signal junction and outputs a description of the delay circuit as the adjustment delay information, the difference being indicated by the adjustment latency information.
6. The semiconductor design support apparatus as claimed in claim 1, wherein the adjustment delay information generating unit deletes, from a block having large latency, a delay circuit corresponding to a difference in signal latency of the blocks at the signal junction and outputs a description of the delay circuit as the adjustment delay information, the difference being indicated by the adjustment latency information.
7. The semiconductor design support apparatus as claimed in claim 1, wherein in the circuit description information, a description of delay circuits is preliminarily provided at a part requiring the delay adjustment, and the adjustment delay information generating unit sets, to “0”, latency of a delay circuit provided for a block having large latency and sets latency of a delay circuit provided for a block having small latency to a difference in signal latency of the blocks at the signal junction, the difference being indicated by the adjustment latency information.
8. The semiconductor design support apparatus as claimed in claim 1, further comprising a circuit generating unit configured to generate a latency-adjusted lower-level circuit from the read circuit description information which is a high-level circuit description and the generated adjustment delay information.
9. A semiconductor design support control method applied to a semiconductor design support apparatus that reads circuit description information and generates information required for delay adjustment, the semiconductor design support control method comprising:
- a logic simulation step of performing logic simulation based on the circuit description information and outputting logic simulation result information;
- a latency information acquiring step of acquiring, from the logic simulation result information, latency information relating to signals at a signal junction, the signals being output from a plurality of blocks;
- an adjustment latency calculating step of calculating, from the latency information, adjustment latency information required for the delay adjustment; and
- an adjustment delay information generating step of generating, from the adjustment latency information, adjustment delay information required for the delay adjustment.
10. A non-transitory computer-readable storage medium storing a semiconductor design support control program for causing a computer to execute a process, the computer constituting a semiconductor design support apparatus that reads circuit description information and generates information required for delay adjustment, the process comprising:
- a logic simulation step of performing logic simulation based on the circuit description information and outputting logic simulation result information;
- a latency information acquiring step of acquiring, from the logic simulation result information, latency information relating to signals at a signal junction, the signals being output from a plurality of blocks;
- an adjustment latency calculating step of calculating, from the latency information, adjustment latency information required for the delay adjustment; and
- an adjustment delay information generating step of generating, from the adjustment latency information, adjustment delay information required for the delay adjustment.
Type: Application
Filed: Feb 25, 2011
Publication Date: Sep 1, 2011
Patent Grant number: 8701061
Applicant: RICOH COMPANY, LTD. (Tokyo)
Inventor: YASUTAKA TSUKAMOTO (Kanagawa)
Application Number: 13/034,971
International Classification: G06F 17/50 (20060101);