Abstract: A thin film transistor array substrate of the present invention having an array area, and a frame area, the thin film transistor array substrate includes: a thin film transistor; an upper metal pattern formed by the same material as source and drain electrodes at the same layer; a transparent conductive film pattern; and an upper layer insulation film, wherein the transparent conductive film pattern has: a first-type transparent conductive film pattern provided to located within one of a pattern of the electrode pattern and a pattern of the metal pattern, as viewed from the top side, and to not cover pattern end faces of the electrode pattern or the metal pattern; and a second-type transparent conductive film pattern provided to stick out from an inside of at least a portion of one of the patterns, as viewed from the top side and to cover the pattern end faces.

Abstract: A thin film transistor array substrate of the present invention having an array area, and a frame area, the thin film transistor array substrate includes: a thin film transistor; an upper metal pattern formed by the same material as source and drain electrodes at the same layer; a transparent conductive film pattern; and an upper layer insulation film, wherein the transparent conductive film pattern has: a first-type transparent conductive film pattern provided to located within one of a pattern of the electrode pattern and a pattern of the metal pattern, as viewed from the top side, and to not cover pattern end faces of the electrode pattern or the metal pattern; and a second-type transparent conductive film pattern provided to stick out from an inside of at least a portion of one of the patterns, as viewed from the top side and to cover the pattern end faces.

Abstract: In a method of manufacturing a TFT substrate in accordance with an exemplary aspect of the present invention, an intrinsic semiconductor film, an impurity semiconductor film, and a conductive film for source lines are formed in succession, and a resist having a thin-film portion and a thick-film portions is formed on the conductive film for source lines. Then, etching is performed by using the resist as a mask, and after that, a part of the conductive film for source lines is exposed by removing the thin-film portion of the resist. Next, the exposed conductive film for source lines is etched by using the thick-film portions of the resist a mask, so that the impurity semiconductor film is exposed. Then, by etching the exposed impurity semiconductor film, a back channel region of a TFT 108 is formed. Further, a dummy back channel region 18a, which is irrelevant to the operation of the finished product, is also formed in a portion other than the TFT 108 region.

Abstract: A method of manufacturing a multilayer thin film pattern includes forming a metal film over a substrate, forming a second thin film over the metal film, forming a resist pattern over the second thin film, etching the second thin film using the resist pattern as a mask, transforming the resist pattern using an organic solvent or a RELACS agent to cover an edge face of the etched second thin film and etching the metal film while the edge face of the second thin film is covered with the resist pattern.

Abstract: In forming a thin film transistor using multi-tone exposure, a wiring width of a foundational wiring is 40 ?m or less, and a ratio of a wiring width of a foundational wiring in a dense case to a space between adjacent wirings is 1.7, preferably 1.0 or less.

Abstract: A method of manufacturing a thin film transistor array substrate according to the present invention includes: forming a pattern made of a first conductive film; stacking a gate insulating film, a semiconductor layer, and a resist in the stated order; forming a resist pattern having a step structure in a thickness direction; forming an exposed area of the first conductive film and a pattern of the semiconductor layer by using the resist pattern; forming a pattern made of a second conductive film in contact with the first conductive film in the exposed area of the first conductive film; and forming a pattern made of a third conductive film. The first conductive film forms a gate electrode, and the second conductive film forms each of a source electrode and a drain electrode. The third conductive film forms a pixel electrode, and the second conductive film is coated with an upper-layer film.

Abstract: An island-like semiconductor layer is formed on a main surface of an insulating substrate. A side wall of the island-like semiconductor layer is made substantially perpendicular to the insulating substrate. An insulating film is formed along the side wall of the semiconductor layer. The insulating film is formed to include a slanted face and have a sectional shape in which a width measured from the side wall of the semiconductor layer decreases as a distance to a bottom increases. A gate insulating film can be formed on the semiconductor layer with good step coverage because of inclusion of the insulating film, to preclude a possibility of causing disconnection of a gate electrode. Also, a thickness of a portion of the semiconductor layer in which a channel region is formed is uniform, to obtain stable transistor characteristics.

Abstract: In a method of manufacturing a TFT substrate in accordance with an exemplary aspect of the present invention, an intrinsic semiconductor film, an impurity semiconductor film, and a conductive film for source lines are formed in succession, and a resist having a thin-film portion and a thick-film portions is formed on the conductive film for source lines. Then, etching is performed by using the resist as a mask, and after that, a part of the conductive film for source lines is exposed by removing the thin-film portion of the resist. Next, the exposed conductive film for source lines is etched by using the thick-film portions of the resist a mask, so that the impurity semiconductor film is exposed. Then, by etching the exposed impurity semiconductor film, a back channel region of a TFT 108 is formed. Further, a dummy back channel region 18a, which is irrelevant to the operation of the finished product, is also formed in a portion other than the TFT 108 region.

Abstract: In forming a thin film transistor using multi-tone exposure, a wiring width of a foundational wiring is 40 ?m or less, and a ratio of a wiring width of a foundational wiring in a dense case to a space between adjacent wirings is 1.7, preferably 1.0 or less.

Abstract: An additional circuit is formed on a glass substrate, and a passivation film is deposited thereon. After an insulation film is deposited on the passivation film, a contact hole is formed, and a signal line is deposited and connected to the additional circuit. After the signal line and the insulation film are patterned, an organic insulation film is formed, to thereby have a surface of an uneven configuration depending on a step formed by the signal line and the insulation film. A reflective electrode is formed on the organic insulation film, to thereby have a surface of an uneven configuration. This eliminates the need to perform a photolithography process step for the formation of the surface of the organic insulation film in the uneven configuration, thereby reducing manufacturing costs.

Abstract: A method of manufacturing a thin film transistor array substrate according to the present invention includes: forming a pattern made of a first conductive film; stacking a gate insulating film, a semiconductor layer, and a resist in the stated order; forming a resist pattern having a step structure in a thickness direction; forming an exposed area of the first conductive film and a pattern of the semiconductor layer by using the resist pattern; forming a pattern made of a second conductive film in contact with the first conductive film in the exposed area of the first conductive film; and forming a pattern made of a third conductive film. The first conductive film forms a gate electrode, and the second conductive film forms each of a source electrode and a drain electrode. The third conductive film forms a pixel electrode, and the second conductive film is coated with an upper-layer film.

Abstract: A thin film transistor substrate includes a thin film transistor of a first conductivity type, a semiconductor layer having a channel region of the first conductivity type placed between the source/drain regions, a gate electrode formed to an opposite face to the semiconductor layer with an gate insulating film interposed therebetween, an opening in the gate electrode corresponding to both edges in a channel width direction of the channel region. In the channel region corresponding to the opening, a highly concentrated impurity region having a higher impurity concentration of the first conductivity type than the channel corresponding to the gate electrode is formed.

Abstract: A semiconductor device comprises a glass substrate serving as a substrate having an insulated surface and a silicon layer located on a position overlapping with this glass substrate. The silicon layer includes an amorphous gettering region. Preferably, the silicon layer includes a main region serving as an active element region, and the gettering region is preferably included in the remaining portion of the silicon layer excluding the main region. Preferably, the silicon layer may include a portion serving as an active region of a thin-film transistor.

Abstract: A method of manufacturing a multilayer thin film pattern includes forming a metal film over a substrate, forming a second thin film over the metal film, forming a resist pattern over the second thin film, etching the second thin film using the resist pattern as a mask, transforming the resist pattern using an organic solvent or a RELACS agent to cover an edge face of the etched second thin film and etching the metal film while the edge face of the second thin film is covered with the resist pattern.

Abstract: A thin film transistor substrate includes a thin film transistor of a first conductivity type, a semiconductor layer having a channel region of the first conductivity type placed between the source/drain regions, a gate electrode formed to an opposite face to the semiconductor layer with an gate insulating film interposed therebetween, an opening in the gate electrode corresponding to both edges in a channel width direction of the channel region. In the channel region corresponding to the opening, a highly concentrated impurity region having a higher impurity concentration of the first conductivity type than the channel corresponding to the gate electrode is formed.

Abstract: An additional circuit is formed on a glass substrate, and a passivation film is deposited thereon. After an insulation film is deposited on the passivation film, a contact hole is formed, and a signal line is deposited and connected to the additional circuit. After the signal line and the insulation film are patterned, an organic insulation film is formed, to thereby have a surface of an uneven configuration depending on a step formed by the signal line and the insulation film. A reflective electrode is formed on the organic insulation film, to thereby have a surface of an uneven configuration. This eliminates the need to perform a photolithography process step for the formation of the surface of the organic insulation film in the uneven configuration, thereby reducing manufacturing costs.

Abstract: It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TRI) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.

Abstract: A thin film transistor device includes: an island shaped semiconductor layer; a metal film that covers at least a part of a source region and a drain region of the semiconductor layer; a gate insulating film that covers the semiconductor layer and the metal film; an interlayer insulating film that covers the gate insulating film; and a signal wire that lies on the interlayer insulating film. The gate insulating film and the interlayer insulating film are formed with contact hole that reaches the metal film. The signal wire is connected to the metal film through the contact hole.

Abstract: An island-like semiconductor layer is formed on a main surface of an insulating substrate. A side wall of the island-like semiconductor layer is made substantially perpendicular to the insulating substrate. An insulating film is formed along the side wall of the semiconductor layer. The insulating film is formed to include a slanted face and have a sectional shape in which a width measured from the side wall of the semiconductor layer decreases as a distance to a bottom increases. A gate insulating film can be formed on the semiconductor layer with good step coverage because of inclusion of the insulating film, to preclude a possibility of causing disconnection of a gate electrode. Also, a thickness of a portion of the semiconductor layer in which a channel region is formed is uniform, to obtain stable transistor characteristics.

Abstract: Impurity ions contained in a semiconductor layer are diffused downwardly from a gate electrode by irradiating laser light from the back surface of a transparent substrate after source-drain regions are formed. Thus, a GOLD structure is formed. Consequently, the GOLD structure is formed by performing a smaller number of processes. Also, variation in characteristics can be suppressed by preventing occurrence of asymmetry between left and right LDD regions.