Abstract: Impurity ions contained in a semiconductor layer are diffused downwardly from a gate electrode by irradiating laser light from the back surface of a transparent substrate after source-drain regions are formed. Thus, a GOLD structure is formed. Consequently, the GOLD structure is formed by performing a smaller number of processes. Also, variation in characteristics can be suppressed by preventing occurrence of asymmetry between left and right LDD regions.

Abstract: An object is to obtain a semiconductor device in which channel length is reduced without increasing the gate resistance to realize higher operation speed and its manufacturing method.

Abstract: It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TR1) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.

Abstract: A semiconductor device capable of holding multibit information in one memory cell, and a method of manufacturing the semiconductor device. A trench is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film of a gate insulating film which interpose the trench are caused to function as first and second electric charge holding portions capable of holding electric charges. In the case in which first electric charges are trapped on the drain side and second electric charges are trapped on the source side, a portion of a gate electrode in the trench functions as a shield. If a fixed potential is given to the gate electrode, the second electric charge holding portion is not influenced by an electric field induced by the first electric charges so that the trapping of the second electric charges is not inhibited.

Abstract: A semiconductor device comprises a glass substrate serving as a substrate having an insulated surface and a silicon layer located on a position overlapping with this glass substrate. The silicon layer includes an amorphous gettering region. Preferably, the silicon layer includes a main region serving as an active element region, and the gettering region is preferably included in the remaining portion of the silicon layer excluding the main region. Preferably, the silicon layer may include a portion serving as an active region of a thin-film transistor.

Abstract: An object is to obtain a semiconductor device in which channel length is reduced without increasing the gate resistance to realize higher operation speed and its manufacturing method.

Abstract: It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TR1) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.

Abstract: A semiconductor device and manufacturing method including a MOSFET having a trench-type element isolation structure (2) formed on a main surface of a semiconductor substrate (1). A pair of extensions (3) and source/drain regions (4) are selectively formed in the main surface so as to face each other through a channel region (50), a silicon oxide film (5) is formed on the trench-type element isolation structure (2) and on the source/drain regions (4) through a silicon oxide film (12), sidewalls (6) are formed on sides of the silicon oxide film (5), a gate insulating film (7) is formed on the main surface in a part where the channel region (50) is formed and a gate electrode (8) is formed to fill a recessed portion in an inversely tapered shape formed by the sides of the sidewalls (6) and the upper surface of the gate insulating film (7).

Abstract: Two source/drain regions (20) belonging to separate elements which are adjacent to each other are connected through a metal layer (14) having the same height as a height of a metal layer (10) forming a part of a gate electrode. In a manufacturing process, an insulating layer (8) is made of other material than and inserted between two insulating layers (7) and (16). The two insulating layers (7) and (16) function as molds for burying the metal layers (10), (14) and (15) therein and made of the same material. The metal layer (14) can therefore be formed at the same height as the height of the metal layer (10). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.

Abstract: Two source/drain regions (20) belonging to separate elements which are adjacent to each other are connected through a metal layer (14) having the same height as a height of a metal layer (10) forming a part of a gate electrode. In a manufacturing process, an insulating layer (8) is made of other material than and inserted between two insulating layers (7) and (16). The two insulating layers (7) and (16)function as molds for burying the metal layers (10), (14) and (15) therein and made of the same material. The metal layer (14) can therefore be formed at the same height as the height of the metal layer (10). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.

Abstract: A semiconductor device and manufacturing method capable of forming shallow extension regions in insulated-gate transistors. A side wall material containing about 1 to 20% of phosphorus, such as PSG, is deposited on the sides of an opening to a film thickness of tens of nanometers to about 100 nm and etched back to form phosphorus-containing side walls respectively adjacent to boron-containing side walls. An interlayer insulating film of silicon nitride etc. is then formed on the silicon nitride film. A thermal process performed during formation of the interlayer insulating film forms N-type extension regions in the NMOS region through a diffusion where phosphorus contained in the phosphorus-containing side walls serves as the diffusion source and P-type extension region in the PMOS region through a diffusion where boron contained in the boron-containing side walls serves as the diffusion source.

Abstract: A semiconductor device includes a silicon substrate (1), a pair of isolating insulation films (9), a channel region (2), a pair of source/drain regions (3), a pair of silicon oxide films (4) formed on an upper surface of the silicon substrate (1) so as to overlie the source/drain regions (3), and a gate structure (8) formed in a first recess defined by the upper surface of the silicon substrate (1) over the channel region (2) and side surfaces of the pair of silicon oxide films (4). The gate structure (8) includes a gate oxide film (5) formed on the upper surface of the silicon substrate (1), a pair of silicon oxide films (6) formed on lower part of the side surfaces of the pair of silicon oxide films (4), and a metal film (7) filling a second recess surrounded by upper part of the side surfaces of the silicon oxide films (4), the silicon oxide films (6) and the gate oxide film (5).

Abstract: An object is to obtain a semiconductor device manufacturing method capable of forming shallow extension regions in insulated-gate transistors. A side wall material containing about 1 to 20% of phosphorus, such as PSG is deposited on the sides of an opening to a film thickness of tens of nanometers to about 100 nm and etched back to form phosphorus-containing side walls (15a) and (15b) respectively adjacent to boron-containing side walls (10a) and (10b). An interlayer insulating film (48) of silicon nitride etc. is then formed on the silicon nitride film (14).

Abstract: An object is to obtain a semiconductor device in which channel length is reduced without increasing the gate resistance to realize higher operation speed and its manufacturing method.

Abstract: A semiconductor device and manufacturing method capable of forming shallow extension regions in insulated-gate transistors. A side wall material containing about 1 to 20% of phosphorus, such as PSG, is deposited on the sides of an opening to a film thickness of tens of nanometers to about 100 nm and etched back to form phosphorus-containing side walls respectively adjacent to boron-containing side walls. An interlayer insulating film of silicon nitride etc. is then formed on the silicon nitride film. A thermal process performed during formation of the interlayer insulating film forms N-type extension regions in the NMOS region through a diffusion where phosphorus contained in the phosphorus-containing side walls serves as the diffusion source and P-type extension region in the PMOS region through a diffusion where boron contained in the boron-containing side walls serves as the diffusion source.

Abstract: There is described a method of manufacturing a semiconductor device, wherein a DRAM memory cell and a logic circuit are fabricated on a single semiconductor substrate, which method enables improvements in the refresh characteristics of the DRAM memory cell by preventing a leakage current from developing and enables improvements in the reliability of the semiconductor device, reduces power consumption, and enables improvements in the performance and processing speed of integrated circuits by assembly of the integrated circuits into a single chip. After formation of a polysilicon layer which is to act as gate electrodes, silicon nitride films are formed so as to cover source/drain regions of the DRAM memory cell and to cause other source/drain regions and the polysilicon layer to be exposed. A metal silicide layer is formed on the semiconductor substrate by means of self-aligned silicide technique.

Abstract: A method of manufacturing a MISFET includes the steps of forming a gate insulation film (2) on a semiconductor substrate (1), forming a dummy gate (3B) made of a material having an etch selectivity relative to the material of the gate insulation film (2) on the gate insulation film (2), implanting an impurity into the semiconductor substrate (1), forming an interlayer insulation film (7), made of a material having an etch selectivity relative to the material of the dummy gate (3B) on a side surface of the dummy gate (3B), etching away the dummy gate (3B), and filling a space in which the dummy gate (3B) has been present with a gate electrode material of metal. Gradually thinning the dummy gate in the step of impurity implantation allows the formation of LDD regions and the patterning of a gate electrode below a minimum patterning size limit of a photolithographic technique.

Abstract: An object is to obtain a method of manufacturing semiconductor devices having trench isolation structure which accomplishes simplification of manufacturing process without deterioration of polishing uniformity. After a silicon oxide film (5) is deposited an HDP-CVD method, a polysilicon film (6) is deposited to such a thickness that the polysilicon film (6) on upper regions of raised areas is removed and the polysilicon film (6) in recessed areas remains in a first CMP process and that the polysilicon film (6) serves as a mask in a later etching process. Subsequently, the first CMP process is performed and the etching process to the silicon oxide film (5) is performed by using the polysilicon film (6) after the first CMP process as a mask to remove the silicon oxide film (5) in the upper regions of the raised areas, and a second CMP process is further performed to planarize the semiconductor substrate (1).

Abstract: There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode.

Abstract: There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode.