Patents by Inventor Yasuyoshi Kaise

Yasuyoshi Kaise has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11322523
    Abstract: To reduce a reduction in the quality of a displayed image in portions corresponding to source lines including detour portions in a display area. Gate lines (20) and source lines (30), which intersect with each other, extend on an insulating substrate (1) so as to detour an opening area (A1). Separated portions (24) are provided as lower shielding electrodes (23) in an inner non-display area (A2) so as to be overlapped with source detour portions (31) of the source lines (30) in a plan view.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 3, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Keiichi Ina, Yasuyoshi Kaise
  • Publication number: 20210341804
    Abstract: A display device includes an array substrate; a counter substrate facing the array substrate; a color filter disposed on the array substrate or the counter substrate, the color filter being composed of a plurality of colored films; a plurality of pixel electrodes disposed on the array substrate and overlapping the plurality of colored films; a common electrode disposed on the array substrate and closer to the counter substrate than the plurality of pixel electrodes are, the common electrode overlapping the plurality of pixel electrodes with an inter-electrode insulating film interposed between the common electrode and the plurality of pixel electrodes; and a conductive light-blocking portion disposed on the array substrate and overlapping at least a color boundary between the plurality of colored films, the conductive light-blocking portion being closer to the counter substrate than the common electrode is, the conductive light-blocking portion being connected to the common electrode.
    Type: Application
    Filed: April 22, 2021
    Publication date: November 4, 2021
    Inventors: YASUHIRO KUROE, NORIYUKI OHASHI, YASUYOSHI KAISE
  • Patent number: 11036106
    Abstract: A decline in the display quality in portion areas corresponding to source lines that run through an inner non-display area in a display area is reduced. The arrangement of source lines that run through an inner non-display area is changed in an upper change area and a lower change area so that the source lines that are simultaneously driven are not adjacent to each other in a display area and are adjacent to each other in a passage area.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 15, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasuyoshi Kaise, Keiichi Ina, Yuhichiroh Murakami, Shige Furuta, Hidekazu Yamanaka
  • Publication number: 20210141277
    Abstract: A decline in the display quality in portion areas corresponding to source lines that run through an inner non-display area in a display area is reduced. The arrangement of source lines that run through an inner non-display area changed in an upper change area and a lower change area so that the source lines that are simultaneously driven are not adjacent to each other in a display area and are adjacent to each other in a passage area.
    Type: Application
    Filed: June 28, 2018
    Publication date: May 13, 2021
    Inventors: Yasuyoshi KAISE, Keiichi INA, Yuhichiroh MURAKAMI, Shige FURUTA, Hidekazu YAMANAKA
  • Patent number: 10928684
    Abstract: A display device includes a color filter substrate, an array substrate, a liquid crystal layer, a protection layer, and a plurality of main spacers. The color filter substrate includes a display region, a hole frame region, and a hole region. Further, in a thickness direction of the hole region of the color filter, an organic flattening film is present on a surface of the array substrate on the color filter substrate side at parts corresponding to positions of the main spacers.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: February 23, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Keiichi Ina, Jin Nakamura, Hisashi Nagata, Isao Takahashi, Yasuyoshi Kaise
  • Publication number: 20200341308
    Abstract: An active matrix substrate is provided that is applicable to high-resolution liquid crystal panels, as well as to low-resolution liquid crystal panels, for improved video quality. An active matrix substrate includes: at least one thin film transistor for each subpixel; and light-blocking layers each overlapping a different group of a prescribed number of the thin film transistors, wherein the prescribed number is double the number of thin film transistors per pixel.
    Type: Application
    Filed: April 22, 2020
    Publication date: October 29, 2020
    Inventor: YASUYOSHI KAISE
  • Patent number: 10802316
    Abstract: The present invention provides a liquid crystal display device which can prevent a camera image from being adversely affected by the birefringence of external polarized light which enters a camera through the liquid crystal layer. In a liquid crystal display device (1A), light to enter a camera (3) passes through a part of a liquid crystal panel (10A). The liquid crystal panel (10A) is configured so that the first part of the liquid crystal layer (14), which first part is located in the camera light transmissive region (S1) allowing the light to enter the camera 3 to pass therethrough, has a retardation R1 represented by the following formula: R1=m? (where (i) m is a positive integer and (ii) ? is a wavelength of the light passing through the liquid crystal layer).
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: October 13, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hisashi Nagata, Yasuyoshi Kaise, Jin Nakamura
  • Publication number: 20200310186
    Abstract: A display device includes a color filter substrate, an array substrate, a liquid crystal layer, a protection layer, and a plurality of main spacers. The color filter substrate includes a display region, a hole frame region, and a hole region. Further, in a thickness direction of the hole region of the color filter, an organic flattening film is present on a surface of the array substrate on the color filter substrate side at parts corresponding to positions of the main spacers.
    Type: Application
    Filed: March 23, 2020
    Publication date: October 1, 2020
    Inventors: KEIICHI INA, JIN NAKAMURA, HISASHI NAGATA, ISAO TAKAHASHI, YASUYOSHI KAISE
  • Publication number: 20200301220
    Abstract: A display device includes a through-hole passing through a display region, a plurality of signal lines, and a plurality of scanning lines. Each of the plurality of signal lines includes a first straight line portion and a first bypass portion. Each of the plurality of scanning lines is wired in a layer different from a layer of the plurality of signal lines, and includes a second straight line portion and a second bypass portion. The first straight line portion of each signal line and the second bypass portion of each scanning line intersect each other in a plan view, and the first bypass portion of each signal line and the second bypass portion of each scanning line are wired in different regions from each other.
    Type: Application
    Filed: March 16, 2020
    Publication date: September 24, 2020
    Inventors: Keiichi INA, Yasuyoshi KAISE
  • Publication number: 20200168633
    Abstract: To reduce a reduction in the quality of a displayed image in portions corresponding to source lines including detour portions in a display area. Gate lines (20) and source lines (30), which intersect with each other, extend on an insulating substrate (1) so as to detour an opening area (A1). Separated portions (24) are provided as lower shielding electrodes (23) in an inner non-display area (A2) so as to be overlapped with source detour portions (31) of the source lines (30) in a plan view.
    Type: Application
    Filed: June 28, 2018
    Publication date: May 28, 2020
    Inventors: KEIICHI INA, YASUYOSHI KAISE
  • Publication number: 20200050036
    Abstract: A display device includes a first substrate, a second substrate disposed opposite the first substrate, pixels arranged in a matrix within a plate surface of the first substrate and the second substrate, a first line disposed on the second substrate and extending in a first direction along the plate surface, a first light blocking section disposed on the first substrate and between the pixels that are next to each other in the first direction and extending in a second direction that is along the plate surface and crosses the first direction, and a second light blocking section disposed on the second substrate and between the pixels that are next to each other in the second direction, extending in the first direction, and overlapping the first line.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 13, 2020
    Inventors: Keiichi INA, Yasuyoshi KAISE
  • Publication number: 20190310501
    Abstract: The present invention provides a liquid crystal display device which can prevent a camera image from being adversely affected by the birefringence of external polarized light which enters a camera through the liquid crystal layer. In a liquid crystal display device (1A), light to enter a camera (3) passes through a part of a liquid crystal panel (10A). The liquid crystal panel (10A) is configured so that the first part of the liquid crystal layer (14), which first part is located in the camera light transmissive region (S1) allowing the light to enter the camera 3 to pass therethrough, has a retardation R1 represented by the following formula: R1=m? (where (i) m is a positive integer and (ii) ? is a wavelength of the light passing through the liquid crystal layer).
    Type: Application
    Filed: April 9, 2019
    Publication date: October 10, 2019
    Inventors: HISASHI NAGATA, YASUYOSHI KAISE, JIN NAKAMURA
  • Publication number: 20190310524
    Abstract: The present invention provides a liquid crystal display device and a method of production thereof, each of which can prevent a camera image from being adversely affected by the birefringence of external polarized light which enters the camera through the liquid crystal layer. In a liquid crystal display device (1A), light to enter a camera (3) passes through a part of a liquid crystal panel (10A). Then, the liquid crystal panel (10A) is configured so that (i) a first part of the liquid crystal layer (14), which first part is located in the camera light transmissive region (S1) (through which the light to enter the camera (3) passes), has an isotropic refractive index and (ii) the second part of the liquid crystal layer (14), which part is located in the non-camera light transmissive region (S2) (which excludes the camera light transmissive region (S1)), has an anisotropic refractive index.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 10, 2019
    Inventors: HISASHI NAGATA, YASUYOSHI KAISE, JIN NAKAMURA
  • Publication number: 20190259349
    Abstract: Luminance unevenness in a display area having an irregular shape is suppressed. A display panel is a display panel in which a cutout is provided, including: a display area in which sub pixels are provided; a non-display zone which is located between the cutout and the display area; a scanning signal line which is provided so as to pass through the display area and the non-display zone; an electric conductor which is at least partially located in the non-display zone; and an insulating film, the scanning signal line being provided so as to overlap with the electric conductor via the insulating film.
    Type: Application
    Filed: December 19, 2018
    Publication date: August 22, 2019
    Inventors: Yasuyoshi KAISE, Keiichi INA, Yoshimizu MORIYA, Ryohji YAYOTANI, Shige FURUTA, Hidekazu YAMANAKA
  • Publication number: 20190259347
    Abstract: A display device includes: an mth scanning signal line to which a plurality of sub pixels are connected; an nth scanning signal line to which a sub pixel is connected, the number of sub pixels which are connected to the nth scanning signal line being lower than the number of sub pixels which are connected to the mth scanning signal line; and a driver circuit which includes a plurality of output circuits and which drives the mth scanning signal line and the nth scanning signal line, an mth one of the plurality of output circuits including an mth output transistor connected to the mth scanning signal line, an nth one of the plurality of output circuits including an nth output transistor connected to the nth scanning signal line, a driving capability of the nth output transistor being lower than that of the mth output transistor.
    Type: Application
    Filed: January 3, 2019
    Publication date: August 22, 2019
    Inventors: Shige FURUTA, Nami NAGIRA, Hidekazu YAMANAKA, Yasuyoshi KAISE, Takahiro YAMAGUCHI, Kohei HOSOYACHI, Yuhichiroh MURAKAMI
  • Patent number: 10203562
    Abstract: A liquid crystal display device according to one aspect of the present invention includes: a liquid crystal layer sandwiched between an element substrate and an opposing substrate; a plurality of spacers; and a Hack matrix provided on a surface on the element substrate side of the opposing substrate and having a first portion that extends in a row direction to separate a plurality of subpixels arranged in a column direction and a second portion that extends in the column direction to separate a plurality of subpixels arranged in the row direction, are included. The first portion is formed by alternately disposing first regions and second regions having a narrower area than the first regions every two subpixels arranged in the row direction. The spacer is disposed in any of the first regions. The spacer in disposed in the first regions. Spacers arranged in odd-numbered rows and spacers arranged in even-numbered rows do not adjoin each other in the column direction.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: February 12, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kaori Saitoh, Yasuyoshi Kaise
  • Publication number: 20180039120
    Abstract: A liquid crystal display device according to one aspect of the present invention includes: a liquid crystal layer sandwiched between an element substrate and an opposing substrate; a plurality of spacers; and a Hack matrix provided on a surface on the element substrate side of the opposing substrate and having a first portion that extends in a row direction to separate a plurality of suhpixels arranged in a column direction and a second portion that extends in the column direction to separate a plurality of subpixels arranged in the row direction, are included. The first portion is formed by alternately disposing first regions and second regions having a narrower area than the first regions every two subpixels arranged in the row direction. The spacer is disposed in any of the first regions. The spacer in disposed in the first regions. Spacers arranged in odd-numbered rows and spacers arranged in even-numbered rows do not adjoin each other in the column direction.
    Type: Application
    Filed: March 3, 2016
    Publication date: February 8, 2018
    Inventors: KAORI SAITOH, YASUYOSHI KAISE
  • Patent number: 9632380
    Abstract: A liquid crystal display device includes a TFT array substrate (first substrate), a counter substrate (second substrate), a liquid crystal layer, and a common electrode (first electrode), an insulating film, and pixel electrodes 21 (second electrode) that are provided on the TFT array substrate. Each of the pixel electrodes 21 has a plurality of linear electrodes 26 and a first connection portion 27. Each of the linear electrodes 26 has a main line portion 29 and a first bent portion 30. An additional capacitance portion 32 is provided integrally with the first connection portion 27 in a region along an arrangement direction of a plurality of first bent portions 30.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: April 25, 2017
    Assignee: SHARP KUBUSHIKI KAISHA
    Inventors: Yuki Kawashima, Yasuyoshi Kaise
  • Patent number: 9366931
    Abstract: The present invention aims to provide a liquid crystal display panel having a structure in which a plurality of gate electrodes are arranged on a continuous semiconductor layer and still capable of suppressing increase of a parasitic capacitance between a source region and a drain region. The liquid crystal display panel of the invention includes a thin film transistor. The thin film transistor includes: a base insulating film; a semiconductor layer extending linearly at least from a first portion to a second portion; a source electrode; a drain electrode; and gate electrodes, respectively, to cover the semiconductor layer with a gate insulating film therebetween. A light shielding film is arranged to cover each projection region corresponding to projection of the gate electrode. The light shielding film is arranged in the form of a plurality of light shielding film elements. The light shielding film elements each cover one or more projection regions.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: June 14, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yasuyoshi Kaise
  • Publication number: 20150277194
    Abstract: First subpixel group and second subpixel group are disposed alternately in a direction orthogonal to a gate bus line. A first subpixel and a second subpixel have shapes axially symmetric about a symmetry axis. Each of a plurality of first subpixels includes a plurality of first strip electrodes inclined by an angle of ? clockwise with respect to a rubbing direction. Each of a plurality of second subpixels includes a plurality of second strip electrodes inclined by an angle of ? counterclockwise with respect to a rubbing direction. Each of a plurality of source bus lines includes a first inclined part inclined by an angle of ? clockwise with respect to a rubbing direction and a second inclined part inclined by an angle of ? counterclockwise with respect to a rubbing direction. A rubbing direction is orthogonal to a gate bus line. Each of a plurality of spacers is disposed in a vicinity of a source bus line and also disposed linearly in parallel with a rubbing direction.
    Type: Application
    Filed: September 30, 2013
    Publication date: October 1, 2015
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Kaori Saitoh, Yasuyoshi Kaise