Abstract: A field effect transistor for a high voltage operation can include vertical current paths, which may include vertical surface regions of a pedestal semiconductor portion that protrudes above a base semiconductor portion. The pedestal semiconductor portion can be formed by etching a semiconductor material layer employing a gate structure as an etch mask. A dielectric gate spacer can be formed on sidewalls of the pedestal semiconductor portion. A source region and a drain region may be formed underneath top surfaces of the base semiconductor portion. Alternatively, epitaxial semiconductor material portions can be grown on the top surfaces of the base semiconductor portions, and a source region and a drain region can be formed therein. Alternatively, a source region and a drain region can be formed within via cavities in a planarization dielectric layer.

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

Abstract: A first field effect transistor and a second field effect transistor are formed on a substrate. A silicon nitride liner is formed over the first field effect transistor and the second field effect transistor. An upper portion of the silicon nitride liner is converted into a thermal silicon oxide liner. A lower portion of the silicon nitride liner remains as a silicon nitride material portion. A first portion of the thermal silicon oxide liner is removed from above the second field effect transistor, and a second portion of the thermal silicon oxide liner remains above the first field effect transistor. Selective presence of the silicon oxide liner provides differential stress within the channels of the first and second field effect transistors, which can be employed to optimize performance of different types of field effect transistors.

Abstract: A control unit includes an excessive output suppression control unit which suppresses an excessive output by reducing a current command value from a host control apparatus. A control signal output unit obtains a motor control signal by adding a reduction amount of the current command value to the current command value. The excessive output suppression control unit includes: an oil pressure estimating unit which estimates oil pressure based on a current and a rotating speed of the electric motor; and a current command value correction amount calculating unit which compares outputs the reduction amount of the current command value if the estimated oil pressure is higher than target oil pressure. One of the target oil pressure and the estimated oil pressure compared by the current command value correction amount calculating unit is corrected based on oil temperature information.

Abstract: In an electric pump system, hydraulic fluid that is stored in an oil pan is supplied to a transmission mechanism through an oil passage by driving an oil pump with the use of a motor. An EOPECU estimates a hydraulic pressure of the hydraulic fluid on the basis of a driving current for the motor and a rotation speed of the motor, and executes drive control on the motor on the basis of the estimated hydraulic pressure value.

Abstract: A control unit includes an excessive output suppression control unit which suppresses an excessive output by reducing a current command value from a host control apparatus. A control signal output unit obtains a motor control signal by adding a reduction amount of the current command value to the current command value. The excessive output suppression control unit includes: an oil pressure estimating unit which estimates oil pressure based on a current and a rotating speed of the electric motor; and a current command value correction amount calculating unit which compares outputs the reduction amount of the current command value if the estimated oil pressure is higher than target oil pressure. One of the target oil pressure and the estimated oil pressure compared by the current command value correction amount calculating unit is corrected based on oil temperature information.

Abstract: The present invention provides a heat-sensitive recording material that has high gloss and excellent absorption and scratch off properties against sebum soiling; and a method for producing the heat-sensitive recording material. More specifically, the present invention provides a heat-sensitive recording material containing a heat-sensitive recording layer, an intermediate layer, and a protective layer, which are sequentially formed in this order on a support. The heat-sensitive recording layer contains a leuco dye and a developer; the intermediate layer contains an aqueous adhesive; and the protective layer is cured by irradiation of an ultraviolet- or electron-beam-curable resin composition with ultraviolet light or an electron beam. The heat-sensitive recording material additionally contains, on the protective layer, an uppermost layer which contains an aqueous adhesive and a pigment having a mean particle diameter of not more than 100 nm.

Abstract: In a method of manufacturing a semiconductor device, first contact holes reaching diffusion regions of a cell transistor, bit line contact holes reaching diffusion regions of the cell transistor, and interconnect grooves communicating with the bit line contact holes are buried in a first insulating film. In addition, first contact plugs and bit line contacts are respectively formed by burying conductive materials in the first contact holes, the bit line contact holes and the interconnect grooves, and the first contact plugs are electrically connected to a capacitor formed in a third insulating film through an opening formed in a second insulating film.

Abstract: A semiconductor device includes: a diffusion layer configuring a memory cell, and a diffusion layer configuring a dummy cell formed over the semiconductor substrate, interlayer insulating films formed over the semiconductor substrate, a cylinder layer insulating film including at least one concavity overlapping a diffusion layer and formed over an interlayer insulating film, a contact plug formed over one diffusion layer, a contact plug formed over another diffusion layer, a lower electrode formed over the side surfaces and bottom surface of the concavity and coupled to the diffusion layer by way of the contact plug, a dielectric material film formed over the lower electrode, over the cylinder layer insulating film and over the contact plug, and coupling by way of the contact plug to the diffusion layer, and an upper electrode formed over the inductive film material.

Abstract: The present invention provides a heat-sensitive recording material that has high gloss and excellent absorption and scratch off properties against sebum soiling; and a method for producing the heat-sensitive recording material. More specifically, the present invention provides a heat-sensitive recording material containing a heat-sensitive recording layer, an intermediate layer, and a protective layer, which are sequentially formed in this order on a support. The heat-sensitive recording layer contains a leuco dye and a developer; the intermediate layer contains an aqueous adhesive; and the protective layer is cured by irradiation of an ultraviolet- or electron-beam-curable resin composition with ultraviolet light or an electron beam. The heat-sensitive recording material additionally contains, on the protective layer, an uppermost layer which contains an aqueous adhesive and a pigment having a mean particle diameter of not more than 100 nm.

Abstract: In a method of manufacturing a semiconductor device, first contact holes reaching diffusion regions of a cell transistor, bit line contact holes reaching diffusion regions of the cell transistor, and interconnect grooves communicating with the bit line contact holes are buried in a first insulating film. In addition, first contact plugs and bit line contacts are respectively formed by burying conductive materials in the first contact holes, the bit line contact holes and the interconnect grooves, and the first contact plugs are electrically connected to a capacitor formed in a third insulating film through an opening formed in a second insulating film.

Abstract: A position recognition device for deciding a zone where a moving object takes a position. The device comprises: a travel distance decider for deciding whether or not the moving object has traveled a predetermined distance corresponding to the detection error of the position of the moving object; and a zone decider for deciding the zone where the moving object takes a position, if the travel distance decider decides that the moving object has traveled the predetermined distance. According to the invention, therefore, “the decision of the zone where the moving object exists” is not made, in case the position of the moving object cannot be precisely detected. Therefore, the precision in the decision of the zone where the moving object exists is improved, and it is unnecessary to set a buffer zone that “the decision of the zone where the moving object exists is not made if the moving object takes a position in the neighborhood” as the reference for deciding the existing zone of the moving object.

Abstract: In a semiconductor device, a semiconductor substrate is sectioned into a logic-circuit formation section in which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed. A multi-layered insulating layer is formed on the substrate, and a conductive structure is formed in the insulating layer at the logic-circuit formation section. Capacitors are formed in the insulating layer at the memory formation section. Each of the capacitors includes a lower capacitor electrode, a capacitor dielectric layer formed on the lower capacitor electrode, and an upper capacitor electrode formed on the capacitor dielectric layer, with upper is end faces of the upper capacitor electrodes being coplanar with an upper end face of the conductive structure. Bit-line layers are formed in the insulating layer below the lower capacitor electrodes at the memory formation section.

Abstract: An on-vehicle automatic charging apparatus 10 obtains its own position information from GPS signals from GPS satellites 51 to 53, determines on the basis of the position information whether conditions for charging are satisfied, and subtracts a calculated charge amount from an inserted prepaid car, when the conditions for charging are satisfied. At this time, information used for calculation of the charge amount is written into the prepaid card as a charge record. When the prepaid card is inserted into a card issuing machine 20 in order to increase the balance, the card issuing machine 20 reads the written charge record and transmits it to a center computer 30. The center computer 30 distributes the charge amount to management companies on the basis of the charge record.

Abstract: In a semiconductor device, a semiconductor substrate is sectioned into a logic-circuit formation section in which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed. A multi-layered insulating layer is formed on the substrate, and a conductive structure is formed in the insulating layer at the logic-circuit formation section. Capacitors are formed in the insulating layer at the memory formation section. Each of the capacitors includes a lower capacitor electrode, a capacitor dielectric layer formed on the lower capacitor electrode, and an upper capacitor electrode formed on the capacitor dielectric layer, with upper is end faces of the upper capacitor electrodes being coplanar with an upper end face of the conductive structure. Bit-line layers are formed in the insulating layer below the lower capacitor electrodes at the memory formation section.

Abstract: A system for charge processing tolls and the like. A vehicle mounted device detects the position of a vehicle 32 using GPS, and transmits position information via a wireless channel to a central station. The central station performs charge processing (calculation) for an area in which a charge is applied based on the position of the vehicle, and transmits the charge to the vehicle mounted device. The vehicle mounted device collects a toll from a prepaid card or IC card or the like on the basis of the received charge processing result.