Abstract: A backlight module for a liquid crystal display includes: LEDs; LED drivers; a controller that outputs data and the latch signal to the LED drivers; data lines for transmitting the data; and latch signal lines for transmitting the latch signal. The latch signal lines are wired according to each of a plurality of first groups obtained by dividing LED drivers. The data lines are wired according to each of a plurality of second groups, which are constructed with a collection of at least one LED driver selected from each of the plurality of first groups without duplication, and each data line is commonly connected to at least one LED belonging to the corresponding second group.

Abstract: A backlight module for a liquid crystal display includes: LEDs; LED drivers; a controller that outputs data and the latch signal to the LED drivers; data lines for transmitting the data; and latch signal lines for transmitting the latch signal. The latch signal lines are wired according to each of a plurality of first groups obtained by dividing LED drivers. The data lines are wired according to each of a plurality of second groups, which are constructed with a collection of at least one LED driver selected from each of the plurality of first groups without duplication, and each data line is commonly connected to at least one LED belonging to the corresponding second group.

Abstract: A backlight module for a liquid crystal display includes: LEDs; LED drivers; a controller that outputs data and the latch signal to the LED drivers; data lines for transmitting the data; and latch signal lines for transmitting the latch signal. The latch signal lines are wired according to each of a plurality of first groups obtained by dividing LED drivers. The data lines are wired according to each of a plurality of second groups, which are constructed with a collection of at least one LED driver selected from each of the plurality of first groups without duplication, and each data line is commonly connected to at least one LED belonging to the corresponding second group.

Abstract: A method for manufacturing an integrated member and an integrated member manufactured by the method which can improve the joining strength and reduce the manufacturing cost. A method for manufacturing an integrated member by welding a first member formed of aluminum alloy material and a second member formed of ferrous-based material characterized in that the first member contains a predetermined amount of silicon and has a thickness larger than that of the second member. The second member can be pressed against the first member along the thickness direction, and by electrically energizing the pressed-in portion during the pressing period, electric resistance welding can be used. The pressing-in amount is set to a value larger than the thickness of the second member and less than that of the first member. The overlapping margin of the first and second members is set to a value of 0.5 mm or more.

Abstract: A method for manufacturing an integrated member and an integrated member manufactured by the method which can improve the joining strength and reduce the manufacturing cost. A method for manufacturing an integrated member by welding a first member formed of aluminum alloy material and a second member formed of ferrous-based material characterized in that the first member contains a predetermined amount of silicon and has a thickness larger than that of the second member. The second member can be pressed against the first member along the thickness direction, and by electrically energizing the pressed-in portion during the pressing period, electric resistance welding can be used. The pressing-in amount is set to a value larger than the thickness of the second member and less than that of the first member. The overlapping margin of the first and second members is set to a value of 0.5 mm or more.

Abstract: A backlight module for a liquid crystal display includes: LEDs; LED drivers; a controller that outputs data and the latch signal to the LED drivers; data lines for transmitting the data; and latch signal lines for transmitting the latch signal. The latch signal lines are wired according to each of a plurality of first groups obtained by dividing LED drivers. The data lines are wired according to each of a plurality of second groups, which are constructed with a collection of at least one LED driver selected from each of the plurality of first groups without duplication, and each data line is commonly connected to at least one LED belonging to the corresponding second group.

Abstract: A method for manufacturing an integrated member and an integrated member manufactured by the method which can improve the joining strength and reduce the manufacturing cost. A method for manufacturing an integrated member by welding a first member formed of aluminum alloy material and a second member formed of ferrous-based material characterized in that the first member contains a predetermined amount of silicon and has a thickness larger than that of the second member. The second member can be pressed against the first member along the thickness direction, and by electrically energizing the pressed-in portion during the pressing period, electric resistance welding can be used. The pressing-in amount is set to a value larger than the thickness of the second member and less than that of the first member. The overlapping margin of the first and second members is set to a value of 0.5 mm or more.

Abstract: An integrated member can comprise different members each formed of materials having different mechanical characteristics. A method for manufacturing such an integrated member can comprise an electric resistance welding step in which the first member is press-fit into the second member and the press-fit portion can be electrically energized to achieve the electric resistance welding so as to integrate the first member and the second member. The method can further comprise a carburized layer forming step in which carburizing-quenching and tempering, or carbonitriding-quenching and tempering, is performed on the integrated member obtained in the electric resistance welding step to form carburized layers therein in accordance with the mechanical characteristics of the first member and the second member.

Abstract: A method for manufacturing an integrated member and an integrated member manufactured by the method which can improve the joining strength and reduce the manufacturing cost. A method for manufacturing an integrated member by welding a first member formed of aluminum alloy material and a second member formed of ferrous-based material characterized in that the first member contains a predetermined amount of silicon and has a thickness larger than that of the second member. The second member can be pressed against the first member along the thickness direction, and by electrically energizing the pressed-in portion during the pressing period, electric resistance welding can be used. The pressing-in amount is set to a value larger than the thickness of the second member and less than that of the first member. The overlapping margin of the first and second members is set to a value of 0.5 mm or more.

Abstract: A display device in which gradation wiring lines of positive polarity included in a (m)th group of wiring lines of positive polarity and gradation wiring lines of positive polarity included in a (m+1)th group of wiring lines of positive polarity are alternately provided, and in which gradation wiring lines of negative polarity included in a (m?)th group of wiring lines of negative polarity and gradation wiring lines of negative polarity included in a (m?+1)th group of wiring lines of negative polarity are alternately provided. The device further includes (n)th resistance dividing circuits of positive polarity which include (m)th resistance dividing circuits connected to the (m)th group of wiring lines of positive polarity, and (m+1)th resistance dividing circuits connected to the (m+1)th group of wiring lines of positive polarity. Resistance dividing circuits of negative polarity are connected in a similar manner to the gradation wiring lines of negative polarity.

Abstract: A data signal loading circuit (i) which includes: a comparator CMP1 receiving clock signal CKP and reverse-phase signal CKN of clock signal CKP, and outputting clock signal CLP1 which is in phase with clock signal CKP, and clock signal CLN 1 having a reverse phase of clock signal CKP; a comparator CMP 2 having a non-inverting input terminal receiving clock signal CLP1, and an inverting input terminal receiving clock signal CLN1; and a comparator CMP3 having an inverting input terminal receiving clock signal CLP 1, and a non-inverting input terminal receiving clock signal CLN 1, and (ii) which, by using output signals CL1 and CL2 of the comparator CMP2 and the comparator CMP3 as clock signals for latch circuits L1 and L2, equalizes delay times for the rise or fall of clock signals CL1 and CL2 inputted to the latch circuits L1 and L2, and (iii) has low power consumption.

Abstract: Gradation wiring lines of positive polarity included in a (m)th group of wiring lines of positive polarity and gradation wiring lines of positive polarity included in a (m+1)th group of wiring lines of positive polarity are alternately provided. Gradation wiring lines of negative polarity included in a (m?)th group of wiring lines of negative polarity and gradation wiring lines of negative polarity included in a (m?+1)th group of wiring lines of negative polarity are alternately provided.

Abstract: A selection section (105) selects a step voltage, among a plurality of step voltages (SV1, SV2, SV3, . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV1, SV2, SV3, . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section (106) amplifies the step voltage selected by the selection section (105). An output section (107) outputs the step voltage amplified by the amplifier section (106) as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).

Abstract: A selection section (105) selects a step voltage, among a plurality of step voltages (SV1, SV2, SV3, . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV1, SV2, SV3, . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section (106) amplifies the step voltage selected by the selection section (105). An output section (107) outputs the step voltage amplified by the amplifier section (106) as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).

Abstract: A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

Abstract: A converter of 6-bit input includes a reference voltage generating circuit generating 17 reference voltages, a first switch circuit having 19 switch pairs each including MOS transistors for selecting two adjacent reference voltages in accordance with the four most significant bits, a second switch circuit including a series circuit of MOS transistors for dividing the selected two reference voltages into four to obtain three intermediate voltages, and a third switch circuit for selectively outputting the lower of the selected two reference voltages or one of the three intermediate voltages. In a second mode in which a gray level having a smaller ON-resistance of a MOS transistor than that in the first mode is selected, the number of MOS transistors used in the first and second switch circuits for voltage division is increased.

Abstract: A data signal loading circuit (i) which includes: a comparator CMP1 receiving clock signal CKP and reverse-phase signal CKN of clock signal CKP, and outputting clock signal CLP1 which is in phase with clock signal CKP, and clock signal CLN 1 having a reverse phase of clock signal CKP; a comparator CMP 2 having a non-inverting input terminal receiving clock signal CLP1, and an inverting input terminal receiving clock signal CLN1; and a comparator CMP3 having an inverting input terminal receiving clock signal CLP 1, and a non-inverting input terminal receiving clock signal CLN 1, and (ii) which, by using output signals CL1 and CL2 of the comparator CMP2 and the comparator CMP3 as clock signals for latch circuits L1 and L2, equalizes delay times for the rise or fall of clock signals CL1 and CL2 inputted to the latch circuits L1 and L2, and (iii) has low power consumption.

Abstract: A converter of 6-bit input includes a reference voltage generating circuit generating 17 reference voltages, a first switch circuit having 19 switch pairs each including MOS transistors for selecting two adjacent reference voltages in accordance with the four most significant bits, a second switch circuit including a series circuit of MOS transistors for dividing the selected two reference voltages into four to obtain three intermediate voltages, and a third switch circuit for selectively outputting the lower of the selected two reference voltages or one of the three intermediate voltages. In a second mode in which a gray level having a smaller ON-resistance of a MOS transistor than that in the first mode is selected, the number of MOS transistors used in the first and second switch circuits for voltage division is increased.

Abstract: In order to correctly hold a low-amplitude input signal even when the operating speed of a display element drive apparatus is high, a differential signal including a pair of CLKP1 and CLKN1 is input to a first comparator and a second comparator in a manner that provides opposite phases between respective output voltage signals. An output of the first comparator is frequency-divided by the first frequency dividing flip-flop, while an output of the second comparator is frequency-divided by the second frequency dividing flip-flop. A first data holding flip-flop holds an input data signal in synchronization with a signal output by a first frequency dividing flip-flop, while a second data holding flip-flop holds an input data signal in synchronization with a signal output by a second frequency dividing flip-flop.

Abstract: A source driver 4A arranged on a liquid crystal panel includes therein in-chip reference voltage wires 17 extending from one end to the other end of an LSI chip. The source driver 4A includes therein: branch reference voltage wires 17a branching off from in-chip reference voltage wires 17; reference voltage production buffers 31; a control circuit 30 for controlling the reference voltage production buffers 31; a reference voltage production resistor section 32 for subdividing the reference voltage into values of n steps; voltage level selection circuits 34 each for selecting one of the subdivided voltages; and output buffers 35. Since the reference voltages are supplied to each source driver 4 via wiring for connecting the in-chip reference voltage wires 17 in series with one another, the wiring structure for supplying the reference voltages can be simplified.