Abstract: A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

Abstract: For example, in order to convert a 6-bit digital signal into an analog signal, a reference voltage generating circuit for generating 17 reference voltages, a first switch circuit having 19 switch pairs each including a MOS transistor for two reference voltages adjacent to each other in accordance with upper four bits, a second switch circuit including a series circuit of 12 MOS transistors and for dividing the difference between the two selected reference voltages using combined ON-resistances into four so as to obtain three intermediate voltages, and a third switch circuit for selectively outputting the lower voltage of the two selected reference voltages or one of the three intermediate voltages in accordance with lower two bits, are provided.

Abstract: A driving device for driving an image display system, which sequentially receives input image data corresponding to gradation of each pixel of a display image and outputs a driving voltage signal includes: an operation section for obtaining output image data of which a bit number is smaller than a bit number of the input image data based on input image data of a target pixel to be processed and input image data of a pixel in vicinity of the target pixel; a reference voltage generation section for generating a plurality of reference voltages of different levels; and a reference voltage selection section for selecting one of the plurality of reference voltages. The operation section is configured to obtain output image data of the target pixel so that a difference between the input image data and output image data of the target pixel and a difference between the input image data and output image data of the pixel in vicinity of the target pixel cancel out each other.

Abstract: A time required for an output voltage of a source follower to rise from Low to a predetermined voltage depends on a bias voltage. Therefore, by setting a converged voltage of an output voltage to be high by increasing the bias voltage, the time required to rise up to the predetermined voltage can be reduced. Therefore, a first source follower which is biased so that the converged value of the output voltage becomes a predetermined Hi voltage when an input data signal goes from Low to Hi, and a second source follower which is biased so as to become the Hi voltage after a period of one clock when an input data signal goes from Low to Hi, are used. The two source followers are operated with appropriate timing.

Abstract: For example, in order to convert a 6-bit digital signal into an analog signal, a reference voltage generating circuit for generating 17 reference voltages, a first switch circuit having 19 switch pairs each including a MOS transistor for two reference voltages adjacent to each other in accordance with upper four bits, a second switch circuit including a series circuit of 12 MOS transistors and for dividing the difference between the two selected reference voltages using combined ON-resistances into four so as to obtain three intermediate voltages, and a third switch circuit for selectively outputting the lower voltage of the two selected reference voltages or one of the three intermediate voltages in accordance with lower two bits, are provided.

Abstract: A receiving circuit receives one or plural first signals involving display from the outside through an input unit. A first transmitting circuit transmits one or plural second signals relevant to the first signal from the first output unit. A second transmitting circuit transmits the second signal from the second output unit.

Abstract: A time required for an output voltage of a source follower to rise from Low to a predetermined voltage depends on a bias voltage. Therefore, by setting a converged voltage of an output voltage to be high by increasing the bias voltage, the time required to rise up to the predetermined voltage can be reduced. Therefore, a first source follower which is biased so that the converged value of the output voltage becomes a predetermined Hi voltage when an input data signal goes from Low to Hi, and a second source follower which is biased so as to become the Hi voltage after a period of one clock when an input data signal goes from Low to Hi, are used. The two source followers are operated with appropriate timing.

Abstract: Each of first and second decoders outputs two voltages each having a voltage value equal to any one of a plurality of gray-level voltages according to gray-level data as two selection voltages or outputs any two of the plurality of gray-level voltages according to gray-level data as the two selection voltages. A connection switching circuit associates one of the first and second decoders with a first differential amplifier and the other decoder with a second differential amplifier. An output switching circuit associates one of the first and second differential amplifiers with a first output node and the other differential amplifier with a second output node. Each of the first and second differential amplifiers synthesizes selection voltages output from the decoder associated with the differential amplifier to generate a driving voltage and outputs the generated driving voltage to the output node associated with the differential amplifier.

Abstract: A compact-size driving voltage controller is provided which can be driven with low power. The compact-size driving voltage controller which can be driven with low power includes a High output operational amplifier and a Low output operational amplifier for supplying driving voltages VcomH, VcomL to a load such as a liquid crystal display panel, an output switch for alternating between the outputs of the operational amplifiers, a Low voltage setting operational amplifier for generating a set voltage to be supplied to the non-inverted input terminal of the Low output operational amplifier, a set voltage generator including a current mirror circuit and a clamping circuit, a bias current controller for controlling the bias current flowing in each operational amplifier with a predetermined timing, and a timing controller for controlling the changeover timing of the output switch.

Abstract: A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

Abstract: In order to correctly hold a low-amplitude input signal even when the operating speed of a display element drive apparatus is high, a differential signal including a pair of CLKP1 and CLKN1 is input to a first comparator and a second comparator in a manner that provides opposite phases between respective output voltage signals. An output of the first comparator is frequency-divided by the first frequency dividing flip-flop, while an output of the second comparator is frequency-divided by the second frequency dividing flip-flop. A first data holding flip-flop holds an input data signal in synchronization with a signal output by a first frequency dividing flip-flop, while a second data holding flip-flop holds an input data signal in synchronization with a signal output by a second frequency dividing flip-flop.

Abstract: In the process of transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, a driving pulse width of a driver switch is feedback-controlled by a clock transmission system (12), whereby the clock signal is transmitted at a small amplitude. A control signal having the pulse width is used for controlling the driver switch in each data transmission system (13), whereby transfer of each data signal at a small amplitude is realized at the same time. Further, in a clock reception system (10), the control signal having the pulse width is used in delay control of a clock delay circuit, whereby an optimum latch timing of received data in each data reception system (11) is realized.

Abstract: A source driver 4A arranged on a liquid crystal panel includes therein in-chip reference voltage wires 17 extending from one end to the other end of an LSI chip. The source driver 4A includes therein: branch reference voltage wires 17a branching off from in-chip reference voltage wires 17; reference voltage production buffers 31; a control circuit 30 for controlling the reference voltage production buffers 31; a reference voltage production resistor section 32 for subdividing the reference voltage into values of n steps; voltage level selection circuits 34 each for selecting one of the subdivided voltages; and output buffers 35. Since the reference voltages are supplied to each source driver 4 via wiring for connecting the in-chip reference voltage wires 17 in series with one another, the wiring structure for supplying the reference voltages can be simplified.

Abstract: A source driver 4A arranged on a liquid crystal panel includes therein in-chip reference voltage wires 17 extending from one end to the other end of an LSI chip. The source driver 4A includes therein: branch reference voltage wires 17a branching off from in-chip reference voltage wires 17; reference voltage production buffers 31; a control circuit 30 for controlling the reference voltage production buffers 31; a reference voltage production resistor section 32 for subdividing the reference voltage into values of n steps; voltage level selection circuits 34 each for selecting one of the subdivided voltages; and output buffers 35. Since the reference voltages are supplied to each source driver 4 via wiring for connecting the in-chip reference voltage wires 17 in series with one another, the wiring structure for supplying the reference voltages can be simplified.

Abstract: In the process of transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, a driving pulse width of a driver switch is feedback-controlled by a clock transmission system (12), whereby the clock signal is transmitted at a small amplitude. A control signal having the pulse width is used for controlling the driver switch in each data transmission system (13), whereby transfer of each data signal at a small amplitude is realized at the same time. Further, in a clock reception system (10), the control signal having the pulse width is used in delay control of a clock delay circuit, whereby an optimum latch timing of received data in each data reception system (11) is realized.

Abstract: First, second, third and fourth inverters are serially connected to form an inverter chain. The first inverter receives a clock input. A first current source is connected to the power supply side of the first inverter. A second current source is connected to the ground side of the third inverter. If the duty ratio of a clock output is lower than a desired value, the magnitude of an electric current in the first current source is decreased such that the falling timing of the clock output is delayed. If the duty ratio of the clock output is higher than a desired value, the magnitude of an electric current in the second current source is decreased such that the rising timing of the clock output is delayed. With such an arrangement, the margins of the setup time and hold time between the clock and data are readily secured.

Abstract: The present invention provides a compact-size driving voltage controller which can be driven with low power. The compact-size driving voltage controller which can be driven with low power includes a High output operational amplifier and a Low output operational amplifier for supplying driving voltages VcomH, VcomL to a load such as a liquid crystal display panel, an output switch for alternating between the outputs of the operational amplifiers, a Low voltage setting operational amplifier for generating a set voltage to be supplied to the non-inverted input terminal of the Low output operational amplifier, a set voltage generator including a current mirror circuit and a clamping circuit, a bias current controller for controlling the bias current flowing in each operational amplifier with a predetermined timing, and a timing controller for controlling the changeover timing of the output switch.

Abstract: It is an object of the present invention to provide a high slew rate differential amplifier circuit that can reduce current consumption while maintaining stability.