Abstract: A solid-state imaging apparatus includes a pixel array, a column processor, and a test signal generating circuit that generates a first digital signal for testing purposes. The test signal generating circuit generates the first digital signal within one horizontal scanning period. The column processor converts a first analog signal, that is converted from the first digital signal, to a second digital signal within the one horizontal scanning period.

Abstract: An imaging device includes: a semiconductor substrate; photoelectric converters which are disposed in the semiconductor substrate; a wiring layer disposed on or above the semiconductor substrate; and at least one capacitor disposed in the wiring layer. The at least one capacitor includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. At least part of the dielectric layer has a trench shape disposed between two adjacent photoelectric converters out of the photoelectric converters in plan view. At least one electrode selected from the group consisting of the first electrode and the second electrode has light-shielding properties.

Abstract: An imaging device includes: a semiconductor substrate; a first photoelectric converter which is disposed in the semiconductor substrate; a second photoelectric converter different from the first photoelectric converter, which is disposed in the semiconductor substrate; a wiring layer disposed on or above the semiconductor substrate; and a capacitor which is disposed in the wiring layer and surrounds the first photoelectric converter in plan view. The capacitor includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The first electrode is connected to one of the first photoelectric converter and the second photoelectric converter.

Abstract: A solid-state imaging apparatus includes a pixel array, a column processor, and a test signal generating circuit that generates a first digital signal for testing purposes. The test signal generating circuit generates the first digital signal within one horizontal scanning period. The column processor converts a first analog signal, that is converted from the first digital signal, to a second digital signal within the one horizontal scanning period.

Abstract: A solid-state imaging apparatus includes a plurality of high-sensitivity pixels that are arranged in a matrix, and perform a photoelectric conversion at a predetermined sensitivity; a plurality of low-sensitivity pixels that are arranged in a matrix in gaps between the plurality of high-sensitivity pixels, and perform a photoelectric conversion at a lower sensitivity than the predetermined sensitivity; and a signal processor that generates a pixel signal by (i) detecting a difference signal between a signal from the plurality of high-sensitivity pixels and a signal from the plurality of low-sensitivity pixels, and (ii) correcting the signal from the plurality of high-sensitivity pixels using the difference signal.

Abstract: A row scanning unit is configured to change a potential of a transfer signal from a second potential V2 to a third potential V3 prior to driving of a transfer operation for causing a transfer of signal charges from a photodiode to a floating diffusion, by supplying a transfer pulse having a first potential V1. The first potential V1 is a positive potential for turning a transfer transistor into ON state, the second potential V2 is a potential for causing pinning of holes under a gate of the transfer transistor and turning the transfer transistor into OFF state, and the third potential V3 is a potential for not causing the pinning of the holes under the gate of the transfer transistor and turning the transfer transistor into OFF state, the third potential being lower than the first potential and higher than the second potential.

Abstract: A digital transmission system includes at least a client device and a transmission device, and rate-adjusts the client signal transmitted from the client device to the transmission device before accommodating/multiplexing the signal in a frame. The transmission device includes a rate adjusting unit and a frame processing unit. The rate adjusting unit encapsulates the client signal by using a predetermined frame structure, inserts an idle pattern if necessary, and performs rate adjustment into the bit rate which can be contained in the frame. The frame processing unit accommodates/multiplexes the signal after the rate adjustment. The digital transmission system inserts a bit string of the client signal directly in a payload area of the digital frame, or accommodates and multiplexes it. Alternatively, a specific pattern is accommodated in the payload area, or accommodated and multiplexed after performing a reversible digital signal processing.

Abstract: According to the present invention, as shown in FIG. 5(a), when a signal for clock recovery ED is generated, which is formed by alternately generating enable periods EN having a ratio (N/M) of N clocks' client data to M clocks' line data and disable periods D1 to D4, a phase of the disable period D2 is advanced by a phase corresponding to the disable period (such as one clock period) during the enable period with reference to phase information added to the signal for clock recovery ED as shown in FIG. 5(c) when a stuff pulse in the line data is detected as indicated by the symbol m0 in FIG. 5(b), thereby generating the signal for clock recovery ED.

Abstract: To provide a cutting tool in which the amount of waste of a main body unit and a cutting head can be suppressed and oscillation at the time of a cutting process can be suppressed. In a cutting tool 100, a helisert 20 made of steel that is lower in rigidity than cemented carbide is provided between an external screw unit 32 and an internal screw unit 11. Accordingly, the external screw unit 32 and the internal screw unit 11 are prevented from being brought into contact with each other, so that a thread 33 of the external screw unit 32 and a thread 12 of the internal screw unit 11 can be prevented from being damaged. Further, oscillation of a cutting head 30 against the main body unit 10 can be absorbed by providing the helisert 20 between the external screw unit 32 and the internal screw unit 11 because steel is lower in rigidity than cemented carbide.

Abstract: A row scanning unit is configured to change a potential of a transfer signal from a second potential V2 to a third potential V3 prior to driving of a transfer operation for causing a transfer of signal charges from a photodiode to a floating diffusion, by supplying a transfer pulse having a first potential V1. The first potential V1 is a positive potential for turning a transfer transistor into ON state, the second potential V2 is a potential for causing pinning of holes under a gate of the transfer transistor and turning the transfer transistor into OFF state, and the third potential V3 is a potential for not causing the pinning of the holes under the gate of the transfer transistor and turning the transfer transistor into OFF state, the third potential being lower than the first potential and higher than the second potential.

Abstract: During the vertical blanking period, first the vertical common signal line switch transistor 213 is turned OFF, then the clamp transistor 218 is turned ON, thereby fixing the sample/hold capacitor 223 to the clamp potential. Also, the column amplifier reset transistor 217 is turned ON, and the column amplifier 216 is reset. Next, the column amplifier reset transistor 217 and the clamp transistor 218 are turned OFF, and the unit column circuit 105 is kept to the clamp state. In this state, the sample/hold transistor 221 is turned OFF, and the sample/hold capacitance 223 is read. The read data is used as the data for correcting the vertical fixed pattern noise.

Abstract: An optical transmission system for performing frequency synchronization even with a client signal with low frequency accuracy, and for transmitting thereof by accommodating/multiplexing without causing a bit slip. A new overhead is added to the entire client signal, and the signal including the new overhead being stuffed is transmitted in conjunction with a plurality of stuffing bits as an optical signal wherein a data storing bit for a negative stuffing, a stuffing information notification bit, and a stuff bits inserting bit for a positive stuffing in the payload are defined in plurality as stuffing bits for adjusting clock frequencies of the client signal in this new overhead.

Abstract: A solid-state image sensor includes: a plurality of pixels, each having a photodiode, a floating diffusion, a transfer transistor, a reset transistor, and an amplifying transistor; vertical signal lines 31 for receiving signals from the plurality of pixels; sampling capacitors 62; circuits 78 for comparing a voltage on a corresponding one of the vertical signal lines 31 with a reference voltage to determine whether the voltage on the corresponding vertical signal line 31 is higher or lower than the reference voltage; and clip circuits 79 for outputting a clip voltage Vclip to a corresponding one of the sampling capacitors 62 based on the output of a corresponding one of the circuits 78. A voltage on each vertical signal line in the state where the signal accumulated in a corresponding photodiode has been transferred to a corresponding floating diffusion, can be used as a comparison voltage of each column.

Abstract: It is an object of the present invention to provide a solid-state imaging device capable of prevent image defects from appearing in an outputted image while suppressing increase in a layout area with a simple circuit structure and is an MOS solid-state imaging device. The MOS solid-state imaging device includes pixels which outputs signals corresponding to intensity of incident light, vertical signal lines which are respectively provided to columns of the pixels and each of which transmits the signals from said pixels in a column direction, and column amplifier circuits that amplify the signals from the pixels and are respectively connected to the vertical signal lines, and each of the column amplifier circuits includes a voltage clipping circuit includes a voltage clipping circuit which limits a maximum output voltage of said column amplifier circuit.

Abstract: A solid-state imaging device comprises a pixel array including a plurality of pixels arranged in rows and columns, and a readout unit operable to read out pixel signals of the pixels included in the pixel array row by row. The readout unit (i) reads out pixel signals of a row of pixels in column order of the pixel array during a horizontal readout period, except during a readout-standby period that is within the horizontal readout period, and (ii) suspends reading out the pixel signals of the row of pixels in the column order during the readout-standby period.

Abstract: A signal generating method and circuit for reducing jitters occurring in a recovered clock signal CK since even when multiple items of specific data are inserted in one cycle of generation period for an enable period, a deviation of an output cycle of the enable period can be eliminated. Accordingly, when a signal for clock recovery ED is generated, which is formed by alternately generating enable periods EN having a ratio (N/M) of N clocks' client data to M clocks' line data and disable periods D1 to D4, a phase of the disable period D2 is advanced by a phase corresponding to the disable period (such as one clock period) during the enable period with reference to phase information added to the signal for clock recovery ED when a stuff pulse in the line data is detected as indicated by the symbol m0, thereby generating the signal for clock recovery ED.

Abstract: A solid-state imaging device according to the present invention includes two-dimensionally arranged unit cells each of which includes a photodiode, a transfer transistor, a floating diffusion, a reset transistor having a source and a drain one of which is connected to the floating diffusion, an amplification transistor, and a selecting transistor, a drain line which is connected to the other one of the source and the drain of the reset transistor and a drain of the amplifying transistor, and a potential switching circuit which is connected to the drain line and sets potential of the floating diffusion to a potential equal to or lower than reset potential by setting potential of the drain line.