Abstract: A digital transmission system includes at least a client device and a transmission device, and rate-adjusts the client signal transmitted from the client device to the transmission device before accommodating/multiplexing the signal in a frame. The transmission device includes a rate adjusting unit and a frame processing unit. The rate adjusting unit encapsulates the client signal by using a predetermined frame structure, inserts an idle pattern if necessary, and performs rate adjustment into the bit rate which can be contained in the frame. The frame processing unit accommodates/multiplexes the signal after the rate adjustment. The digital transmission system inserts a bit string of the client signal directly in a payload area of the digital frame, or accommodates and multiplexes it. Alternatively, a specific pattern is accommodated in the payload area, or accommodated and multiplexed after performing a reversible digital signal processing.

Abstract: A solid-state image sensor includes: a plurality of pixels, each having a photodiode, a floating diffusion, a transfer transistor, a reset transistor, and an amplifying transistor; vertical signal lines 31 for receiving signals from the plurality of pixels; sampling capacitors 62; circuits 78 for comparing a voltage on a corresponding one of the vertical signal lines 31 with a reference voltage to determine whether the voltage on the corresponding vertical signal line 31 is higher or lower than the reference voltage; and clip circuits 79 for outputting a clip voltage Vclip to a corresponding one of the sampling capacitors 62 based on the output of a corresponding one of the circuits 78. A voltage on each vertical signal line in the state where the signal accumulated in a corresponding photodiode has been transferred to a corresponding floating diffusion, can be used as a comparison voltage of each column.

Abstract: An optical transmission system for performing frequency synchronization even with a client signal with low frequency accuracy, and for transmitting thereof by accommodating/multiplexing without causing a bit slip. A new overhead is added to the entire client signal, and the signal including the new overhead being stuffed is transmitted in conjunction with a plurality of stuffing bits as an optical signal wherein a data storing bit for a negative stuffing, a stuffing information notification bit, and a stuff bits inserting bit for a positive stuffing in the payload are defined in plurality as stuffing bits for adjusting clock frequencies of the client signal in this new overhead.

Abstract: It is an object of the present invention to provide a solid-state imaging device capable of prevent image defects from appearing in an outputted image while suppressing increase in a layout area with a simple circuit structure and is an MOS solid-state imaging device. The MOS solid-state imaging device includes pixels which outputs signals corresponding to intensity of incident light, vertical signal lines which are respectively provided to columns of the pixels and each of which transmits the signals from said pixels in a column direction, and column amplifier circuits that amplify the signals from the pixels and are respectively connected to the vertical signal lines, and each of the column amplifier circuits includes a voltage clipping circuit includes a voltage clipping circuit which limits a maximum output voltage of said column amplifier circuit.

Abstract: A solid-state imaging device comprises a pixel array including a plurality of pixels arranged in rows and columns, and a readout unit operable to read out pixel signals of the pixels included in the pixel array row by row. The readout unit (i) reads out pixel signals of a row of pixels in column order of the pixel array during a horizontal readout period, except during a readout-standby period that is within the horizontal readout period, and (ii) suspends reading out the pixel signals of the row of pixels in the column order during the readout-standby period.

Abstract: A parallel precoder circuit executes an EXOR operation on an n-row parallel input, and outputs an n-row parallel output, where 2?n. Outputs of EXOR circuits each of which having a largest column number from among EXOR circuits disposed in first to (n?1)th rows become first-row to (n?1)th-row parallel outputs, respectively. A output of an nth-row delay circuit becomes an nth-row parallel output.

Abstract: A parallel precoder circuit executes an EXOR operation on an n-row parallel input, and outputs an n-row parallel output, where 2?n. Outputs of EXOR circuits each of which having a largest column number from among EXOR circuits disposed in first to (n?1)th rows become first-row to (n?1)th-row parallel outputs, respectively. A output of an nth-row delay circuit becomes an nth-row parallel output.

Abstract: A video display system is disclosed, which includes a display device including a plurality of display cells arranged in an X-Y matrix form, a video signal source for supplying a digital video signal, a pulse width modulator connected to the video signal source for deriving a PWM signal corresponding to the brightness level of the digital video signal, the pulse width modulator including a counter supplied with the digital video signal as a datum signal and a clock signal generator for supplying a clock signal to the counter, and a signal supplying circuit connected to the pulse width modulator for supplying the PWM signal to the display device and reproducing a picture thereon. In this case, the video display system of this invention further includes a control circuit connected to the clock signal generator for changing the frequency of the clock signal supplied to the counter and controlling the brightness of the picture reproduced on the display device.