Patents by Inventor Yasuyuki Hotta

Yasuyuki Hotta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080138701
    Abstract: It is made possible to provide a battery-integrated semiconductor module containing a small built-in battery having satisfactory output characteristics. A battery-integrated semiconductor module includes: an insulating substrate; a semiconductor device provided on the insulating substrate; a nonaqueous electrolyte battery for driving the semiconductor device, which is provided in and/or on the insulating substrate and comprises a positive electrode, a negative electrode, a separator for separating the positive electrode and the negative electrode from each other, and a nonaqueous electrolyte containing an ionic liquid as a main component, with which the positive electrode, the negative electrode, and the separator are impregnated; and a sealing resin provided to cover the semiconductor device and the nonaqueous electrolyte battery, wherein any one of the positive electrode, the negative electrode, and the separator is in contact with the insulating substrate and the sealing resin.
    Type: Application
    Filed: August 23, 2007
    Publication date: June 12, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi Kuboki, Takashi Kishi, Yasuyuki Hotta, Satoshi Mikoshiba, Tomoko Eguchi, Tsuyoshi Kobayashi
  • Patent number: 7370412
    Abstract: An electronic device connecting method according to a first aspect of the present invention includes: mounting an electronic device having at least one electrode portion on a sheet-like porous member having a hole therein so that the electrode portion is close to the porous member; selectively irradiating a predetermined region of the porous member, on which the electronic device is mounted, with energy lines to form a latent image in an irradiated or non-irradiated portion of the porous member, the predetermined region including a portion close to the electrode portion; after irradiating with the energy lines, filling a conductive material in a hole of the latent image of the porous member to form a conductive portion; and bonding and integrating the porous member, in which the conductive portion is formed, to and with the electronic device.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: May 13, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Mitsuyoshi Endo, Naoko Yamaguchi, Yasuyuki Hotta, Shigeru Matake, Hideo Aoki, Misa Sawanobori
  • Patent number: 7329458
    Abstract: Disclosed is a wiring member comprising a sheet-like porous substrate provided with a large number of open-cells which are three-dimensionally branched and opened to a first major surface as well as to a second major surface of the porous substrate, and a conductive portion formed on the first major surface of the porous substrate and formed at least partially an inter-penetrating structure together with the porous substrate at an interface of the porous substrate. The apertures of the open-cells on the first major surface have an average diameter and an average number of the apertures, at least one of which is smaller than that of the second major surface.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: February 12, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Yasuyuki Hotta, Shigeru Matake, Misa Sawanobori, Kou Yamada
  • Publication number: 20080026252
    Abstract: According to one embodiment, there is provided a method of manufacturing a magnetic recording media including depositing a magnetic layer on a substrate and processing the magnetic layer to form protruded magnetic patterns, depositing a planarizing layer in recesses between the magnetic patterns and on the magnetic patterns, and forming steps on a surface of the planarizing layer.
    Type: Application
    Filed: July 27, 2007
    Publication date: January 31, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Sonoda, Tsutomu Nakanishi, Yasuyuki Hotta
  • Patent number: 7312621
    Abstract: A semiconductor test unit comprises a test circuit for inputting/outputting a test signal to/from an examined electronic product, a test signal wiring electrically connected to the test circuit, a contact board electrically connected to an electrode of the examined electronic product and provided with an electrically conductive via to which the test signal is transmitted, a multilayer circuit board electrically connected to the conductive via and the test signal wiring, located under the bottom face of the contact board, and provided with at least one through-hole, and a vacuum attachment mechanism for attaching thereto and holding the examined electronic product, the contact board, and the multilayer circuit board by vacuum. The contact board is made of an insulative material, has top and bottom faces, and is provided with at least one through-hole.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: December 25, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yamaguchi, Yoshiaki Sugizaki, Hideo Aoki, Toshiro Hiraoka, Yasuyuki Hotta, Shigeru Matake, Misa Sawanobori
  • Publication number: 20070146576
    Abstract: A liquid crystal display includes a pair of substrates having main surfaces respectively, the main surfaces facing on each other; a polymer layer interposed between the pair of substrates, the polymer layer including a block copolymer having a liquid crystalline side chain and having a periodic structure in a perpendicular direction to the main surfaces; and a controller that controls a light reflectance of the polymer layer by applying a voltage to the polymer layer.
    Type: Application
    Filed: December 28, 2006
    Publication date: June 28, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Rei HASEGAWA, Haruhi Oooka, Yasuyuki Hotta
  • Publication number: 20060231525
    Abstract: A pattern forming material contains a block copolymer or graft copolymer and forms a structure having micro polymer phases, in which, with respect to at least two polymer chains among polymer chains constituting the block copolymer or graft copolymer, the ratio between N/(Nc?No) values of monomer units constituting respective polymer chains is 1.4 or more, where N represents total number of atoms in the monomer unit, Nc represents the number of carbon atoms in the monomer unit, No represents the number of oxygen atoms in the monomer unit.
    Type: Application
    Filed: June 20, 2006
    Publication date: October 19, 2006
    Inventors: Koji Asakawa, Toshiro Hiraoka, Yoshihiro Akasaka, Yasuyuki Hotta
  • Patent number: 7097781
    Abstract: A pattern forming material contains a block copolymer or graft copolymer and forms a structure having micro polymer phases, in which, with respect to at least two polymer chains among polymer chains constituting the block copolymer or graft copolymer, the ratio between N/(Nc?No) values of monomer units constituting respective polymer chains is 1.4 or more, where N represents total number of atoms in the monomer unit, Nc represents the number of carbon atoms in the monomer unit, No represents the number of oxygen atoms in the monomer unit.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: August 29, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Toshiro Hiraoka, Yoshihiro Akasaka, Yasuyuki Hotta
  • Patent number: 7090784
    Abstract: A pattern forming material contains a block copolymer or graft copolymer and forms a structure having micro polymer phases, in which, with respect to at least two polymer chains among polymer chains constituting the block copolymer or graft copolymer, the ratio between N/(Nc-No) values of monomer units constituting respective polymer chains is 1.4 or more, where N represents total number of atoms in the monomer unit, Nc represents the number of carbon atoms in the monomer unit, No represents the number of oxygen atoms in the monomer unit.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: August 15, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Toshiro Hiraoka, Yoshihiro Akasaka, Yasuyuki Hotta
  • Patent number: 6977130
    Abstract: A method of manufacturing an electronic circuit satisfying demands for cost reduction, diversified small-quantity production, and a shorter cycle of design, manufacture, evaluation, correction, and so on is provided. The method includes at least forming a first pattern or forming a second pattern. Forming the first pattern comprises: forming a visible image on an electrostatic latent image formed on a photosensitive base, by the adhesion of charged particles essentially made of a resin; transferring the visible image onto the intermediate transfer base by the contact and pressurization of the visible image; heating/softening on the intermediate transfer base; and transferring a heated/softened resin layer onto a base material by the contact and pressurization of the resin layer.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: December 20, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Aoki, Chiaki Takubo, Atsuko Iida, Yasuyuki Hotta, Naoko Yamaguchi
  • Patent number: 6906423
    Abstract: A mask used for exposing a porous substrate to form a first region and a second region, the first region being filled with a conductive material piercing through the entire thickness of the porous substrate to constitute an interfacial conductive portion, the second region being filled with a conductive material not piercing the entire thickness of the porous substrate to constitute a non-interfacial conductive portion. The mask includes a first light-transmitting region for exposing the first region, and a second light-transmitting region for exposing the second region, said second light-transmitting region including an aggregation of fine patterns of which an average aperture ratio is not more than 50% of an average aperture ratio of the first light-transmitting region and a size of said fine patterns of the second light-transmitting region being in the range of 0.1 ?m to 10 ?m.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: June 14, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Yasuyuki Hotta, Shigeru Matake, Toshiro Hiraoka
  • Patent number: 6899999
    Abstract: Disclosed is a method of manufacturing a composite member having a conductive pattern, comprising (1) forming on a surface of an insulating body a photosensitive layer containing both a photosensitive compound forming an ion-exchange group upon irradiation with an energy beam and a crosslinkable compound having a crosslinkable group, (2) forming a pattern of ion-exchange groups by selectively exposing the photosensitive layer to an energy beam so as to form an ion-exchange group in the exposed portion, (3) crosslinking the crosslinkable compound contained in at least the exposed portion of the photosensitive layer, (4) allowing metal ions, or a metal colloid to be adsorbed on the pattern of ion-exchange groups formed by the selectively exposing, and (5) forming a composite member having conductive pattern by depositing a conductive material on the pattern of ion-exchange groups having the metal ions, or the metal colloid adsorbed thereon using an electroless plating.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: May 31, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Koji Asakawa, Yasuyuki Hotta, Shigeru Matake
  • Publication number: 20050024067
    Abstract: According to one aspect of the invention, a contact sheet for testing electronic parts, comprising an insulating porous layer; and a connection electrode which is disposed on the insulating porous layer and electrically connect the electrode or terminal of the electronic parts and the terminal of a test apparatus; wherein the connection electrode is embedded below at least one main surface of the insulating porous layer.
    Type: Application
    Filed: July 8, 2004
    Publication date: February 3, 2005
    Inventors: Naoko Yamaguchi, Hideo Aoki, Chiaki Takubo, Toshiro Hiraoka, Yasuyuki Hotta, Shigeru Matake
  • Patent number: 6835889
    Abstract: The present invention provides a composite material such as a passive element, a passive element composite component, a substrate with a built-in passive element and a composite wiring substrate which are free from, for example, a layer peeling problem and enables high density packaging with ease. In the present invention, a porous base material is divided into plural functional regions and a material having different electromagnetic characteristics is filled in a pore of the porous base material of each functional region, to form a passive element or a wiring substrate. Among the aforementioned plural functional regions, at least one functional region is a conductive material region filled with a conductive material and other regions are filled with a high-dielectric material, a high-permeability material or a low-dielectric material.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: December 28, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Yasuyuki Hotta, Koji Asakawa, Shigeru Matake
  • Publication number: 20040205402
    Abstract: A semiconductor test unit comprises a test circuit for inputting/outputting a test signal to/from an examined electronic product, a test signal wiring electrically connected to the test circuit, a contact board electrically connected to an electrode of the examined electronic product and provided with an electrically conductive via to which the test signal is transmitted, a multilayer circuit board electrically connected to the conductive via and the test signal wiring, located under the bottom face of the contact board, and provided with at least one through-hole, and a vacuum attachment mechanism for attaching thereto and holding the examined electronic product, the contact board, and the multilayer circuit board by vacuum. The contact board is made of an insulative material, has top and bottom faces, and is provided with at least one through-hole.
    Type: Application
    Filed: March 31, 2003
    Publication date: October 14, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoko Yamaguchi, Yoshiaki Sugizaki, Hideo Aoki, Toshiro Hiraoka, Yasuyuki Hotta, Shigeru Matake, Misa Sawanobori
  • Publication number: 20040197487
    Abstract: A method of manufacturing an electronic circuit satisfying demands for cost reduction, diversified small-quantity production, and a shorter cycle of design, manufacture, evaluation, correction, and so on is provided. The method includes at least forming a first pattern or forming a second pattern. Forming the first pattern comprises: forming a visible image on an electrostatic latent image formed on a photosensitive base, by the adhesion of charged particles essentially made of a resin; transferring the visible image onto the intermediate transfer base by the contact and pressurization of the visible image; heating/softening on the intermediate transfer base; and transferring a heated/softened resin layer onto a base material by the contact and pressurization of the resin layer.
    Type: Application
    Filed: July 15, 2003
    Publication date: October 7, 2004
    Inventors: Hideo Aoki, Chiaki Takubo, Atsuko Iida, Yasuyuki Hotta, Naoko Yamaguchi
  • Publication number: 20040191497
    Abstract: Disclosed is a wiring member comprising a sheet-like porous substrate provided with a large number of open-cells which are three-dimensionally branched and opened to a first major surface as well as to a second major surface of the porous substrate, and a conductive portion formed on the first major surface of the porous substrate and formed at least partially an inter-penetrating structure together with the porous substrate at an interface of the porous substrate. The apertures of the open-cells on the first major surface have an average diameter and an average number of the apertures, at least one of which is smaller than that of the second major surface.
    Type: Application
    Filed: October 29, 2003
    Publication date: September 30, 2004
    Inventors: Toshiro Hiraoka, Yasuyuki Hotta, Shigeru Matake, Misa Sawanobori, Kou Yamada
  • Publication number: 20040112633
    Abstract: An electronic device module comprises a wiring substrate having an insulating substrate with a porous structure including continuous pores and wiring conductors selectively formed in the porous structure; and an electronic device directly connected to said wiring conductors formed in the porous structure.
    Type: Application
    Filed: September 5, 2003
    Publication date: June 17, 2004
    Inventors: Mitsuyoshi Endo, Toshiro Hiraoka, Yasuyuki Hotta, Hideo Aoki, Hideko Mukaida, Naoko Yamaguchi
  • Patent number: 6709806
    Abstract: Disclosed is a method of manufacturing a composite member in which a conductive portion is selectively formed in an insulator. The method comprises the steps of forming a photosensitive composition layer containing a compound forming an ion-exchange group upon irradiation with light having a wavelength not shorter than 280 nm within or on the surface of an insulator, exposing selectively the photosensitive composition layer to light having a wavelength not shorter than 280 nm, forming an ion-exchange group in the exposed portion, and bonding a metal or metal ions to the ion-exchange group formed in the exposed portion of the photosensitive composition layer.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: March 23, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuyuki Hotta, Toshiro Hiraoka, Koji Asakawa, Shigeru Matake
  • Publication number: 20040050816
    Abstract: A pattern forming material contains a block copolymer or graft copolymer and forms a structure having micro polymer phases, in which, with respect to at least two polymer chains among polymer chains constituting the block copolymer or graft copolymer, the ratio between N/(Nc−No) values of monomer units constituting respective polymer chains is 1.4 or more, where N represents total number of atoms in the monomer unit, Nc represents the number of carbon atoms in the monomer unit, No represents the number of oxygen atoms in the monomer unit.
    Type: Application
    Filed: January 22, 2003
    Publication date: March 18, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Asakawa, Toshiro Hiraoka, Yoshihiro Akasaka, Yasuyuki Hotta