Abstract: Methods for making a semiconductor device using an improved BARC (bottom anti-reflective coating) are provided herein. The improved BARC comprises a polymer formed from at least a styrene monomer having at least one or two hydrophilic substituents. The monomer(s) and substituents can be varied as desired to obtain a balance between film adhesion and wet etch resistance. Also provided is a semiconductor device produced using such methods.

Abstract: Methods for making a semiconductor device using an improved BARC (bottom anti-reflective coating) are provided herein. The improved BARC comprises a polymer formed from at least a styrene monomer having at least one or two hydrophilic substituents. The monomer(s) and substituents can be varied as desired to obtain a balance between film adhesion and wet etch resistance. Also provided is a semiconductor device produced using such methods.

Abstract: Methods for making a semiconductor device using an improved BARC (bottom anti-reflective coating) are provided herein. The improved BARC comprises a polymer formed from at least a styrene monomer having at least one or two hydrophilic substituents. The monomer(s) and substituents can be varied as desired to obtain a balance between film adhesion and wet etch resistance. Also provided is a semiconductor device produced using such methods.

Abstract: A silver nanowire (SNW) protection layer structure includes a substrate; a SNW layer, disposed on the substrate and covering only a partial region of a surface of the substrate, the SNW layer including a plurality of SNW channels; and a SNW protection layer, disposed on the SNW layer and covering a region corresponding to the plurality of SNW channels, the SNW protection layer including a light-resistant antioxidant. A manufacturing method for the SNW protection layer structure above is further provided. The SNW protection layer structure and the manufacturing method thereof are applicable in a touch sensor.

Abstract: A silver nanowire (SNW) protection layer structure includes a substrate; a SNW layer, disposed on the substrate and covering only a partial region of a surface of the substrate, the SNW layer including a plurality of SNW channels; and a SNW protection layer, disposed on the SNW layer and covering a region corresponding to the plurality of SNW channels, the SNW protection layer including a light-resistant antioxidant. A manufacturing method for the SNW protection layer structure above is further provided. The SNW protection layer structure and the manufacturing method thereof are applicable in a touch sensor.

Abstract: An unlocking bracket includes a fastener and an unlocking member. The fastener includes a fixing case and a support rod provided on the fixing case. The support rod is configured to bear on a connector. The fixing case is configured to sleeve on the connector. The unlocking member includes a cantilever and an unlocking block. The cantilever is configured to be rotationally mounted on the fixing case. The unlocking block is configured to abut a locking clip of the connector. The cantilever is configured to drive the unlocking block to rotate to push a locking clip of the connector.

Abstract: An unlocking bracket includes a fastener and an unlocking member. The fastener includes a fixing case and a support rod provided on the fixing case. The support rod is configured to bear on a connector. The fixing case is configured to sleeve on the connector. The unlocking member includes a cantilever and an unlocking block. The cantilever is configured to be rotationally mounted on the fixing case. The unlocking block is configured to abut a locking clip of the connector. The cantilever is configured to drive the unlocking block to rotate to push a locking clip of the connector.

Abstract: The present disclosure relates to a display device including a backlight circuit, a processing circuit, and a clock generation circuit. The backlight circuit is configured to be driven in response to a control signal. The processing circuit is electrically connected to the backlight circuit and is configured to generate a voltage signal and the control signal. The clock generating circuit is electrically connected to the processing circuit to receive the voltage signal. The processing circuit is configured to adjust the control signal according to a clock frequency of the clock signal.

Abstract: An electronic device, including an antenna, includes a pixel array, a control circuit, and a gate driver. The control circuit is coupled with the antenna, and configured to receive a RF signal from the antenna. The gate driver is coupled with the control circuit and the pixel array, and includes multiple shift registers. Each of the multiple shift registers is configured to output a scan signal to the pixel array. The control circuit is configured to output a triggering signal to a first-stage shift register of the multiple shift registers. When the control circuit receives the RF signal, the triggering signal has a triggering pulse. When the first-stage shift register receives the triggering pulse, the first-stage shift register outputs the scan signal having an enabling voltage level.

Abstract: A display system includes a pixel array, an antenna, a reader circuit, and a gate driver circuit. The antenna is configured to transmit a radio frequency (RF) signal in response to a wireless communication. The reader circuit is coupled to the antenna and is configured to receive the RF signal. The gate driver circuit is coupled to the reader circuit and the pixel array. The reader circuit is further configured to generate a clock signal according to the RF signal and transmit the clock signal to the gate drive circuit. The gate driver circuit is configured to generate scanning signals according to the clock signal and transmit the scanning signals to the pixel array.

Abstract: A display system includes a pixel array, an antenna, a reader circuit, and a gate driver circuit. The antenna is configured to transmit a radio frequency (RF) signal in response to a wireless communication. The reader circuit is coupled to the antenna and is configured to receive the RF signal. The gate driver circuit is coupled to the reader circuit and the pixel array. The reader circuit is further configured to generate a clock signal according to the RF signal and transmit the clock signal to the gate drive circuit. The gate driver circuit is configured to generate scanning signals according to the clock signal and transmit the scanning signals to the pixel array.

Abstract: An electronic device, including an antenna, includes a pixel array, a control circuit, and a gate driver. The control circuit is coupled with the antenna, and configured to receive a RF signal from the antenna. The gate driver is coupled with the control circuit and the pixel array, and includes multiple shift registers. Each of the multiple shift registers is configured to output a scan signal to the pixel array. The control circuit is configured to output a triggering signal to a first-stage shift register of the multiple shift registers. When the control circuit receives the RF signal, the triggering signal has a triggering pulse. When the first-stage shift register receives the triggering pulse, the first-stage shift register outputs the scan signal having an enabling voltage level.

Abstract: A semiconductor device comprises a fin shaped structure, a shallow trench isolation, a diffusion break structure and a gate electrode. The fin shaped structure is disposed on a substrate. The shallow trench isolation is disposed in the substrate and surrounds the fin shaped structure. The diffusion break structure is disposed in the fin shaped structure, and the gate electrode is disposed across the fin shaped structure.

Abstract: A semiconductor device comprises a fin shaped structure, a shallow trench isolation, a diffusion break structure and a gate electrode. The fin shaped structure is disposed on a substrate. The shallow trench isolation is disposed in the substrate and surrounds the fin shaped structure. The diffusion break structure is disposed in the fin shaped structure, and the gate electrode is disposed across the fin shaped structure.

Abstract: A display panel includes a display area first and second gate line driving circuits. The display area includes a plurality of pixels is configured to determine how to process a data transmitted on a data line according to first and second control signals transmitted on first and second gate lines respectively and a second control signal transmitted on a second gate line and determine when to emit light according to a light emitting control signal transmitted on a light emitting control line. The first gate line driving circuit is coupled to the first gate line and for providing the first control signal thereto. The second gate line driving circuit is coupled to the second gate line and the light emitting control line and configured to provide the second control signal and the light emitting control signal thereto, respectively.

Abstract: An electrostatic discharge (ESD) protection device includes a first trigger element and a first silicon control rectifier (SCR) element. The first trigger element has a first parasitic bipolar junction transistor (BJT) formed in a substrate. The first SCR element has a second parasitic BJT formed in the substrate. The first parasitic BJT and the second parasitic BJT has a common parasitic bipolar base, and the first parasitic BJT has a trigger voltage substantially lower than that of the second parasitic BJT.

Abstract: A display panel includes a display area first and second gate line driving circuits. The display area includes a plurality of pixels is configured to determine how to process a data transmitted on a data line according to first and second control signals transmitted on first and second gate lines respectively and a second control signal transmitted on a second gate line and determine when to emit light according to a light emitting control signal transmitted on a light emitting control line. The first gate line driving circuit is coupled to the first gate line and for providing the first control signal thereto. The second gate line driving circuit is coupled to the second gate line and the light emitting control line and configured to provide the second control signal and the light emitting control signal thereto, respectively.

Abstract: An electrostatic discharge (ESD) protection device includes a first trigger element and a first silicon control rectifier (SCR) element. The first trigger element has a first parasitic bipolar junction transistor (BJT) formed in a substrate. The first SCR element has a second parasitic BJT formed in the substrate. The first parasitic BJT and the second parasitic BJT has a common parasitic bipolar base, and the first parasitic BJT has a trigger voltage substantially lower than that of the second parasitic BJT.

Abstract: An electrostatic discharge protection structure comprises an isolation layer, a high voltage P-well, an N-well, a P-well, a first doped region of N-type conductivity, a second doped region of P-type conductivity, a third doped region of N-type conductivity, a fourth doped region of P-type conductivity, an anode, and a cathode. The isolation layer is disposed on a substrate. The high voltage P-well is disposed on the isolation layer. The N-well is disposed in the high voltage P-well. The P-well is disposed in the high voltage P-well, and the P-well is separated from the N-well. The first and the second doped regions are disposed in the N-well. The third and the fourth doped regions are disposed in the P-well. The anode is electrically connected to the first doped region and the second doped region, and the cathode is electrically connected to the fourth doped region.

Abstract: A display panel includes a control circuit and a pixel structure. The control circuit selectively provides a data signal or a first reference voltage signal. The pixel structure includes a capacitor, a first, a second and a third switch unit. For the first switch unit, a first and a second terminal are coupled to two the capacitor in series, and a control terminal receives a control signal. For the second switch unit, a first terminal is coupled to the second terminal of the first switch unit, and the control terminal receives a first scan signal. For the third switch unit, a first terminal receives the data or first reference voltage signal, a second terminal is coupled to the second terminal of the second switch unit and a light emitting element, and the control terminal is coupled to the second terminal of the first switch unit.