Abstract: A storage controller interface includes, on a disk controller side of the storage controller interface, a first transceiver circuit configured to transfer a first block of user data to a read channel during a write operation, and a gate transmit circuit configured to, subsequent to the first block of user data being transferred, assert a gate signal to flush the first block of user data from the read channel. The storage controller interface further includes, on a read channel side of the storage controller interface, a second transceiver circuit configured to receive the first block of user data, a gate receive circuit configured to receive the gate signal, and a write fault transceiver circuit configured to selectively assert a write fault signal if the gate transmit circuit does not assert the gate signal subsequent to the first block of user data being transferred to the read channel.

Abstract: An integrated circuit configured to perform finite impulse response filtering on a signal transmitted via a communication channel, the integrated circuit including an encoder and a plurality of filter stages. The encoder is configured to generate a logic signal corresponding to the signal transmitted via the communication channel. The plurality of filter stages is configured to filter the logic signal. Each of the plurality of filter stages includes a respective delay element. Each of the respective delay elements is configured to delay a corresponding portion of the logic signal. Two or more first delay elements of the plurality of delay elements are configured to apply a fixed delay. A second delay element of the plurality of delay elements is configured to apply a variable delay that is based on a signal strength of the corresponding portion of the logic signal.

Abstract: A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design suitable for equalizing receive signals with bit rates above 10 GHz, making it feasible to employ decision feedback equalization in silicon-based optical transceiver modules.

Abstract: A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design suitable for equalizing receive signals with bit rates above 10 GHz, making it feasible to employ decision feedback equalization in silicon-based optical transceiver modules.

Abstract: A system includes a hard disk controller configured to, using only a single pin, transfer serial information from the hard disk controller. The serial information includes control data associated with control of both write operations and read operations. The serial information includes a first bit indicating a start of the control data, a predetermined number of bits of the control data following the first bit, and a second bit indicating an end of the predetermined number of bits of the control data. A read/write channel is configured to receive the serial information and perform the write operations and the read operations based on the serial information.

Abstract: A finite impulse response (FIR) filter apparatus including: an input configured to receive a first input signal; a plurality of coefficient taps configured to filter the first input signal; a plurality of delay elements arranged between the plurality of coefficient taps, the plurality of delay elements configured to delay the first input signal, wherein at least one of the plurality of delay elements is configured to provide a variable delay; and a processor configured to i) determine signal strengths of respective portions of the first input signal, and ii) in response to determining the signal strengths, set the variable delay to skip filtering selected portions of the first input signal.

Abstract: A read circuit including a bit detector, a synchronization mark detector, and a clock generator. The bit detector is configured to output serial bit data including a plurality of bits according to a first clock signal and stored digital data. The synchronization mark detector is configured to detect a synchronization marker in the serial bit data and output a synchronization pulse in response to the synchronization marker. The clock generator is configured to receive the first clock signal and divide the first clock signal to provide a divided clock output based on the synchronization pulse.

Abstract: An interface configured to support a signaling protocol between a first hardware component and a second hardware component. The interface comprises a first pin, a second pin, and a third pin. The first pin is configured to provide a write clock signal sourced from the first hardware component to the second hardware component during a write operation. The second pin is configured to receive a read clock signal sourced from the second hardware component during a read operation. The third pin is configured to transfer serial control information from the first hardware component to the second hardware component during both the read operation and the write operation. Only the third pin is used to transfer the serial control information. The serial control information includes control information for both the read operation and the write operation.

Abstract: In a method for causing data to be written to a non-volatile medium, first data to be encoded and written in a sector of the non-volatile medium as a codeword is transmitted to a write or read/write channel device, and a write gate signal corresponding to the sector is asserted. Asserting the write gate signal indicates to the write or read/write channel device when to write the codeword to the sector. While asserting the write gate signal to cause the codeword to be written, second data to be encoded and written to the non-volatile medium is transmitted to the write or read/write channel device.

Abstract: A read circuit for providing multi-bit disk data to a disk controller in correspondence to analog data from a disk head, includes a low frequency clock generator whose phase is adjustable in response to a detection of the synchronization marker in the analog disk data. A high frequency clock is phase-locked to the output of the disk head, and synchronizes operation of an A/D converter and a bit detector which produces a verified single-bit based on the A/D output. A serial-to-parallel converter converts the single bit output from the bit detector to a parallel output, and the parallel output is latched to multi-bit disk data for use by the disk controller in accordance with a low frequency clock. The low frequency clock is generated by a clock generator from the high frequency clock with a phase that is adjustable in response to the synchronization mark detector.

Abstract: FIR filter apparatus comprises an input responsive to an input signal and an FIR filter that comprises three filter stages. A first delay circuit has a first time delay coupled between two of the three filter stages. A second delay circuit has a second time delay coupled between another two of the three filter stages. The first time delay and second time delay are different.

Abstract: In a method for causing data to be written to a non-volatile medium, first data to be encoded and written in a sector of the non-volatile medium as a codeword is transmitted to a write or read/write channel device, and a write gate signal corresponding to the sector is asserted. Asserting the write gate signal indicates to the write or read/write channel device when to write the codeword to the sector. While asserting the write gate signal to cause the codeword to be written, second data to be encoded and written to the non-volatile medium is transmitted to the write or read/write channel device.

Abstract: An FIR filter apparatus comprises a coefficient generator to generate first and second coefficients. A first end of a shared wiring is coupled to the coefficient generator. A first memory is coupled to a second end of the shared wiring to store the first coefficient in response to a selector. A first multiplier is responsive to the first coefficient stored in the first memory and an input. A first delay circuit is responsive to the input. A second memory is coupled to the second end of the shared wiring to store the second coefficient in response to the selector. A second multiplier is responsive to the second coefficient stored in the second memory and the first delay element.

Abstract: A finite impulse response (FIR) filter comprises a first multiplier that receives an input signal and a first tap coefficient. A first delay element receives the input signal and provides a fixed delay. A second multiplier receives a second tap coefficient and an output of the first delay element. A variable delay element receives the input signal and provides a variable delay. M delay elements provide the fixed delay. A first one of the M delay elements receives an output of the variable delay element and remaining ones of the M delay elements receive an output of a preceding one of the M delay elements, where M is an integer greater than one. M multipliers receive outputs of respective ones of the M delay elements and respective ones of M tap coefficients. A plurality of summers sum outputs of the first, second and M multipliers.

Abstract: A method selects a period of delay in an FIR filter having (i) a plurality of delay elements and (ii) a plurality of coefficient taps each associated with a portion of an input signal in corresponding stages of delay from a corresponding delay element, in which at least one delay element has a period of delay that is selectable. The method includes measuring components of an input signal so as to identify a sequence of components that are smaller than another sequence of larger components. The method includes setting the selectable period of delay to prevent application of the identified sequence of smaller components of the input signal to the coefficient taps.

Abstract: An interface supports a signaling protocol between a first hardware component and a second hardware component. The interface includes a first pin to provide a first clock signal sourced from the first hardware component to the second hardware component during a first operation, the first operation being an operation in which data is being transferred from the first hardware component to the second hardware component. A second pin to receive a second clock signal sourced from the second hardware component during a second operation, the second operation being an operation in which data is being transferred from the second hardware component to the first hardware component. A third pin to provide a first gate control signal sourced from the first hardware component to the second hardware component, the first gate control signal to synchronize data transfer between the first hardware component and the second hardware component during both the first operation and the second operation.

Abstract: In a method for causing data to be written to a non-volatile medium, an indication of a size of a sector or a sector fragment may be transmitted to a channel device, and an indication of a size of a codeword to be written in the sector may be transmitted to the channel device. Data to be iteratively encoded and written in the sector as the codeword may be transmitted to the channel device. A write gate signal corresponding to the sector or the sector fragment may be transmitted to the channel device to indicate to the channel device when to write to the sector or the sector fragment.

Abstract: A finite impulse response (FIR) filter includes a coefficient generator that generates M coefficients, where M is an integer greater than one, M storage elements each storing one of the M coefficients, and a bus. A selector circuit selectively connects the coefficient generator to the M storage elements one at a time via the bus to update the coefficients of the M storage elements.

Abstract: A system includes a read/write channel and a hard disk controller. The hard disk controller includes a latency-independent interface that communicates with the read/write channel. A serial control data circuit transmits a serial control data signal including serial control data, wherein the serial control data signal has a variable number m of words, wherein each of said m words comprises n bits, and wherein at least one of said n bits of each of said m words includes information indicating whether a subsequent word of said serial control data signal will follow. A data circuit that transmits or receives data under the control of the serial control data signal.

Abstract: A system includes a read/write channel and a hard disk controller. The hard disk controller includes a latency-independent interface that communicates with the read/write channel. A serial control data circuit transmits a serial control data signal including serial control data, wherein the serial control data signal has a variable number m of words, wherein each of said m words comprises n bits, and wherein at least one of said n bits of each of said m words includes information indicating whether a subsequent word of said serial control data signal will follow. A data circuit that transmits or receives data under the control of the serial control data signal.