Abstract: An evaluation device and method for orientation estimation for two sensor units arranged on an object. The method including: ascertaining a sensor transformation matrix from a first sensor coordinate system fixed to a first sensor unit into a second sensor coordinate system fixed to a second sensor unit; transforming a first acceleration vector measured using the first sensor unit into the second sensor coordinate system; and defining a first axis {tilde over (x)} located in the second sensor coordinate system, corresponds to a first coordinate x of an object coordinate system extending through the first sensor unit and the second sensor unit, the object coordinate system being fixed to the object, based on the second angular velocity vector, its time derivative, and a difference vector between a second acceleration vector measured using the second sensor unit minus the first acceleration vector transferred into the second sensor coordinate system.

Abstract: A multi-gate HEMT includes at least two gates, with at least one recessed the same depth or at a deeper depth in a barrier layer than at least one other gate. Recessing a gate decreases the thickness of the barrier layer beneath the gate, reducing a density of high mobility carriers in a two-dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of a barrier layer and a buffer layer below the recessed gate. The recessed gate can increase gate control of the 2DEG conductive channel. The multi-gate HEMT has at least one gate recessed the same depth or a deeper depth into the buffer layer than another gate, which forms at least two different turn-on voltages for different gates. This can achieve improvement of transconductance linearity and a positive shift of the threshold voltage.

Abstract: In various embodiments, software architecture and network topology are provided to implement a decentralized distributed computing environment. In some embodiments, the novel network topology is configured as a mesh network such that individual hub devices are connected directly or indirectly with each other. An individual worker can be added to or removed from this network via connection with the hub devices without affecting the rest of the workers in the network and without user intervention or knowledge.

Abstract: Systems and methods for exchanging synchronization information between processing units using a synchronization network are disclosed. The disclosed systems and methods include a device including a host and associated neural processing units. Each of the neural processing units can include a command communication module and a synchronization communication module. The command communication module can include circuitry for communicating with the host device over a host network. The synchronization communication module can include circuitry enabling communication between neural processing units over a synchronization network. The neural processing units can be configured to each obtain a synchronized update for a machine learning model. This synchronized update can be obtained at least in part by exchanging synchronization information using the synchronization network. The neural processing units can each maintain a version of the machine learning model and can synchronize it using the synchronized update.

Abstract: A system includes a high-bandwidth inter-chip network (ICN) that allows communication between neural network processing units (NPUs) in the system. For example, the ICN allows an NPU to communicate with other NPUs on the same compute node (server) and also with NPUs on other compute nodes (servers). Communication can be at the direct memory access (DMA) command level and at the finer-grained load/store instruction level. The ICN system and the programming model allows NPUs in the system to communicate without using a traditional network (e.g., Ethernet) that uses a relatively narrow and slow Peripheral Component Interconnect Express (PCIe) bus.

Abstract: Embodiments of the present invention provide a polishing ring assembly suitable for polishing an electrostatic chuck and method of using the same. In one embodiment, the polishing ring assembly has a retaining ring assembly and an electrostatic chuck fixture. The retaining ring assembly includes an inner diameter and a top surface, a plurality of outer drive rings wherein the plurality of outer drive rings are placed on the top surface of the ceramic retaining ring. The electrostatic chuck fixture includes an electrostatic chuck drive plate adjacent to the inner diameter of in the ceramic retaining ring. The electrostatic chuck drive plate has a lock to secure retaining ring assembly with the electrostatic chuck fixture without transferring the weight from one assembly over to the other through the locking mechanism.

Abstract: Various embodiments facilitate a user to program and control one or more devices through a control system. In some embodiments, an interface is provided to enable the user to manipulate one or more program elements graphically. The one or more program elements include a first program element corresponding to the task, and a user input is provided by the user through a user manipulation of the first program element in the interface. The user manipulation comprises drag and drop, voice control, gesture control and/or any other mode of control. In those embodiments, the user input is then converted a first code understandable to the control system. The first code is then transmitted to the control system through a communication protocol. After the first code is received, a first instruction is generated by the control system and is transmitted to an end device for execution by the first instruction.

Abstract: An apparatus includes first and second compute-in-memory (CIM) arrays. The first CIM array is configured to store weights corresponding to a filter tensor, to receive a first set of activations corresponding to a first receptive field of an input, and to process the first set of activations with the weights to generate a corresponding first tensor of output values. The second CIM array is configured to store a first copy of the weights corresponding to the filter tensor and to receive a second set of activations corresponding to a second receptive field of the input. The second CIM array is also configured to process the second set of activations with the first copy of the weights to generate a corresponding second tensor of output values. The first and second compute-in-memory arrays are configured to process the first and second receptive fields in parallel.

Abstract: Disclosed herein are transconductance circuits, as well as related methods and devices. In some embodiments, a transconductance circuit may include an amplifier having a first input coupled to a voltage input of the transconductance circuit, and a switch coupled between an output of the amplifier and a second input of the amplifier.

Abstract: Certain aspects provide a circuit for in-memory computation. The circuit generally includes an in-memory computation array having a plurality of computation circuits, each of the computation circuits being configured to perform a dot product computation. In certain aspects, each of the computation circuits includes a memory cell, a capacitive element, a precharge transistor coupled between an output of the memory cell and the capacitive element, and a read transistor coupled between a read bit line (RBL) and the capacitive element.

Abstract: A bit cell circuit of a most-significant bit (MSB) of a multi-bit product generated in an array of bit cells in a compute-in-memory (CIM) array circuit is configured to receive a higher supply voltage than a supply voltage provided to a bit cell circuit of another bit cell corresponding to another bit of the multi-bit product. A bit cell circuit receiving a higher supply voltage increases a voltage difference between increments of an accumulated voltage, which can increase accuracy of an analog-to-digital converter determining a pop-count. A bit cell circuit of the MSB in the CIM array circuit receives the higher supply voltage to increase accuracy of the MSB which increases accuracy of the CIM array circuit output. A capacitance of a capacitor in the bit cell circuit of the MSB is smaller to avoid an increase in energy consumption due to the higher voltage.

Abstract: A cooktop includes a power adjustment switch with power grades, a power detection apparatus, a control apparatus, and an adjustment apparatus. The power detection apparatus for detects a power grade to determine an operation period of the power grade and a power level corresponding to the power grade and outputting operation information including the operation period and the power level. The control apparatus calculates a first valid period based on the operation information, and determines whether the first valid period exceeds a first threshold period. When affirmative, the control apparatus outputs adjustment information for adjusting the power grade to reduce the power level. The adjustment apparatus adjusts the power grade based on the adjustment information to reduce the power level. The cooktop actively detects an operating status and adjusts a power grade, to avoid dry burning and potential safety risks.

Abstract: A calibration and verification system for a directional sensor, comprising an industrial control computer and a directional sensor, wherein the industrial control computer is connected to a sensor signal acquisition system, a first triaxial Helmholtz coil and a second triaxial Helmholtz coil, respectively, wherein a heating calibration turntable is disposed in the first triaxial Helmholtz coil and configured to heat and calibrate the directional sensor, and wherein a high-precision inclination and azimuth test turntable is disposed in the second triaxial Helmholtz coil and configured to verify the directional sensor.

Abstract: An integrated device that includes a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, where the first plurality of channels is located between the first source and the first drain; at least one inner spacer located between two adjacent channels from the first plurality of channels; at least two voids located between the two adjacent channels; and a first gate surrounding the first plurality of channels.

Abstract: Certain aspects of the present disclosure relate to a semiconductor device (e.g., a gate-all-around (GAA) semiconductor device) comprising at least one superlattice fin. One example superlattice fin includes a first plurality of nanosheets composed of a first semiconductor material and a second plurality of nanosheets composed of a second semiconductor material, the second semiconductor material being different from the first semiconductor material, wherein a width of a first nanosheet in the first plurality of nanosheets differs from a width of a second nanosheet in the second plurality of nanosheets, the second nanosheet being adjacent to the first nanosheet.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device implemented with multiple channels in a gate-all-around (GAA) high-electron-mobility transistor (HEMT) and techniques for fabricating such a device. One example semiconductor device generally includes a substrate; a first gate layer disposed above the substrate; a first barrier layer disposed above the first gate layer; a first channel region disposed above the first barrier layer; a second barrier layer disposed above the first channel region; a second gate layer disposed above the second barrier layer; a third barrier layer disposed above the second gate layer; a second channel region disposed above the third barrier layer; a fourth barrier layer disposed above the second channel region; a source region; and a drain region.

Abstract: Disclosed herein are transconductance circuits, as well as related methods and devices. In some embodiments, a transconductance circuit may include an amplifier having a first input coupled to a voltage input of the transconductance circuit, and a switch coupled between an output of the amplifier and a second input of the amplifier.

Abstract: A low cost capacitor (e.g., metal-insulator-metal (MIM) capacitor) is included in the back-end-of-line layers for effective routing and area savings. The capacitor has a first electrode (e.g., a first terminal of the capacitor) including a conductive back-end-of-line (BEOL) layer and a second electrode (e.g., a second terminal of the capacitor) including a nitride-based metal. The capacitor also has an etch stop layer (e.g., a dielectric of the capacitor) between the first electrode and the second electrode.

Abstract: Certain aspects of the present disclosure relate to a semiconductor device (e.g., a gate-all-around (GAA) semiconductor device) comprising at least one superlattice fin. One example superlattice fin includes a first plurality of nanosheets composed of a first semiconductor material and a second plurality of nanosheets composed of a second semiconductor material, the second semiconductor material being different from the first semiconductor material, wherein a width of a first nanosheet in the first plurality of nanosheets differs from a width of a second nanosheet in the second plurality of nanosheets, the second nanosheet being adjacent to the first nanosheet.