Abstract: Aspects generally relate to tuning a guard ring in an integrated circuit. A guard ring with a gap surrounds a circuit. The level of isolation provided by the guard ring at a particular frequency can be adjusted by coupling a tuning circuit cross the gap of the guard ring. If the circuit in the guard ring is an inductive circuit the level of inductance at a particular frequency can be adjusted by selecting the appropriate tuning circuit across the gap of the guard ring.

Abstract: Embodiments described herein provide various examples of an automatic obstacle avoidance system for unmanned vehicles using embedded stereo vision techniques. In one aspect, an unmanned aerial vehicle (UAV) capable of performing autonomous obstacle detection and avoidance is disclosed. This UAV includes: a stereo vision camera set coupled to the one or more processors and the memory to capture a sequence of stereo images; and a stereo vision module configured to: receive a pair of stereo images captured by a pair of stereo vision cameras; perform a border cropping operation on the pair of stereo images to obtain a pair of cropped stereo images; perform a sub sampling operation on the pair of cropped stereo images to obtain a pair of sub sampled stereo images; and perform a dense stereo matching operation on the pair of sub sampled stereo images to generate a dense three-dimensional (3D) point map of a space corresponding to the pair of stereo images.

Abstract: A method for operating a gas sensor device, which is equipped with at least one gas-sensitive electrical sensor resistor, a heating element for the controlled heating of the sensor resistor, a detection element for detecting the resistance value of the sensor resistor, and a signal processing element for processing measuring signals. In the method, measurements are carried out in time intervals, in which the resistance value of the sensor resistor is detected as a measuring signal, and the sensor resistor is heated for each measurement, the heating element being operated discontinuously in heating intervals and each measurement being assigned a heating interval. Measurements are automatically carried out in predefinable time intervals, and additional measurements are initiatable at arbitrary times. The duration of the heating intervals assigned to the individual measurements being selected as a function of the time interval to the preceding heating interval.

Abstract: An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.

Abstract: Certain aspects of the present disclosure provide a transistor device, such as a fin field-effect transistor (finFET) device, and techniques for fabrication thereof. One example transistor device generally includes one or more semiconductor channel regions and a metal region disposed above the one or more semiconductor channel regions. The metal region has one or more gaps (e.g., air gaps) disposed therein.

Abstract: A Field-Effect Transistor (FET) with a negative capacitance layer to increase power density provides a negative capacitor connected in series with a conventional positive capacitor. The dimensions of the negative capacitor are controlled to allow the difference in capacitances between the negative capacitor and the positive capacitor to approach zero, which in turn provides a large total capacitance. The large total capacitance provides for increased power density.

Abstract: Various embodiments of a vision-based privacy-preserving embedded fall-detection system are disclosed. This embedded fall-detection system can include one or more cameras for capturing video images of one or more persons. Moreover, this embedded fall-detection system can include various fall-detection modules for processing the captured video images including: a pose-estimation module, an action-recognition module, and a fall-detection module, all of which can perform the intended fall-detection functionalities within the embedded system environment in real-time in order to detect falls of the one or more persons. When a fall is detected, instead of sending the original captured images, the embedded fall-detection system can transmit sanitized video images to the server, wherein each detected person is represented by a skeleton figure in place of the actual person images, thereby preserving the privacy of the detected person.

Abstract: Embodiments described herein provide various examples of a real-time face-detection, face-tracking, and face-pose-selection subsystem within an embedded vision system. In one aspect, a process for identifying near-duplicate-face images using this subsystem is disclosed. This process includes the steps of: receiving a determined best-pose-face image associated with a tracked face when the tracked face is determined to be lost; extracting an image feature from the best-pose-face image; computing a set of similarity values between the extracted image feature and each of a set of stored image features in a feature buffer, wherein the set of stored image features are extracted from a set of previously transmitted best-pose-face images; determining if any of the computed similarity values is above a predetermined threshold; and if no computed similarity value is above the predetermined threshold, transmitting the best-pose-face image to a server and storing the extracted image feature into the feature buffer.

Abstract: A capacitor includes first conductive fingers interdigitated with second conductive fingers at an Mx interconnect level, and third conductive fingers interdigitated with fourth conductive fingers at an Mx-1 interconnect level. The third conductive fingers are offset from the first conductive fingers. The second conductive fingers are offset from the fourth conductive fingers. The capacitor further includes fifth conductive fingers interdigitated with sixth conductive fingers at an Mx-2 interconnect level. The fifth conductive fingers are offset from the third conductive fingers. The sixth conductive fingers are offset from the fourth conductive fingers. The capacitor further includes seventh conductive fingers interdigitated with eighth conductive fingers at an Mx-3 interconnect level. The seventh conductive fingers are offset from the fifth conductive fingers. The eighth conductive fingers are offset from the sixth conductive fingers.

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

Abstract: A co-wound resistor with a low parasitic inductance includes a first resistive strip having an input and a second resistive strip having an output. The second resistive strip has a similar shape as the first resistive strip. The second resistive strip is co-wound in a same direction as the first resistive strip. The second resistive strip and the first resistive strip are configured to generate a mutual inductance that cancels an inductance of the first resistive strip and the second resistive strip. The first interconnect coupling the first resistive strip to the second resistive strip. The first resistive strip, the second resistive strip and the first interconnect are on a same level.

Abstract: A transistor comprises a substrate, a first buffer layer on the substrate, a source region, a drain region, and a channel region on the first buffer layer, a gate on the channel region, a source contact, and a drain contact. The source contact is configured to contact at least three sides of the source region and the drain contact is configured to contact at least three sides of the drain region to lower contact resistance in the source region and in the drain region.

Abstract: A capacitor has reduced misalignment in the interconnect layers and lower capacitance variance. The capacitor includes a first endcap having a first section and a second section orthogonal to the first section. The capacitor includes a first set of conductive fingers orthogonally coupled to the first section. The capacitor includes a third set of conductive fingers orthogonally coupled to the second section of the endcap and a second endcap parallel to the first section of the endcap. The capacitor includes a second set of conductive fingers orthogonally coupled to a second endcap and interdigitated with the first set of conductive fingers at a first interconnect layer. The capacitor includes a third endcap parallel to the second section of the first endcap and a fourth set of conductive fingers orthogonally coupled to the third endcap and interdigitated with the third set of conductive fingers at the first interconnect layer.

Abstract: A method for detecting a gaseous substance in a gas-mixture, a first measuring-variable which represents a first chemical and/or physical parameter of the gas-mixture being acquired, at least one second measuring-variable which represents a second chemical and/or physical parameter of the gas-mixture that differs from the first parameter being acquired, and a starting-measuring-instant, corresponding to the starting-instant, of the first parameter is specified when an amount of a time-derivative of the first measuring-variable exceeds a first predefined threshold-value and an amount of a time-derivative of the second measuring-variable exceeds a second predefined threshold-value, and at least one further first measuring-variable is acquired, an end instant is specified when the at least one further first measuring-variable corresponds to the starting measuring-variable, and an output signal is generated when the amount of a difference between the end instant and the starting instant is greater than a predefin

Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor may include a first semiconductor structure and a gate stack on the first semiconductor structure. The gate stack may include a gate dielectric layer on the first semiconductor structure, a work function material on the gate dielectric layer, and a gate metal fill material on the work function material of the gate stack. The gate metal fill material may include a low resistivity carbon alloy. A dielectric fill material may be included on the gate stack.

Abstract: Certain aspects of the present disclosure provide a memory implemented using negative capacitance material. One example memory generally includes a transistor coupled to a word-line of the memory and a bit-line of the memory, and a capacitive element coupled to the transistor. The capacitive element may include a first layer of dielectric material and a second layer of negative capacitance material, the first layer and the second layer being between a first non-insulative region coupled to the transistor and a second non-insulative region.

Abstract: A resistor-capacitor (RC) delay circuit includes a first capacitor at a first level, a resistor at a second level and a second capacitor at a third level. The second capacitor is electrically connected in parallel with the first capacitor. The second capacitor has a footprint within a footprint of the first capacitor. The resistor is coupled in shunt with the first capacitor and the second capacitor.

Abstract: Certain aspects of the present disclosure provide an integrated circuit (IC) that includes at least one of a via-based vertical capacitor structure or a via-based vertical resistor structure. The IC includes a substrate oriented in a horizontal plane, electrically conductive layers disposed above the substrate, and electrically insulative layers disposed above the substrate and interposed between the plurality of electrically conductive layers. At least one of the vertical capacitor structure or the vertical resistor structure is disposed in the electrically conductive layers and the electrically insulative layers.