Abstract: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact.

Abstract: The present invention relates to the structure and fabrication process of a high-gain monocrystal Silicon Carbide phototransistor applicable at high temperature. In view of the optical gain and applicable temperature of the conventional n-p-n type Silicon Carbide phototransistor are too low for practical usage, the present invention utilizes a newly developed n-i-p-i-n structure to strengthen the intrinsic properties of the element, in order to enhance optical gain of the phototransistor for being able to operate at high temperature steadily.

Abstract: An infrared optical field effect transistor has been developed using a thin film of Lead Titanate (PbTiO3) deposited on a n/p+ Si substrate by RF magnetron sputtering. This transistor possesses excellent pyroelectric properties and can, therefore, be operated even at room temperature. The infrared optical field effect transistor has the following features associated with rapid bulk channel structure and higher mobility: 1. Can be operated at room temperature, unlike quantum type IR sensors which can only operate at very low temperature (−100° C.˜−200° C.), which results in higher costs. 2. High speed response with only 2.3 &mgr;s of rise time. This is much faster than other types of thermal infrared optical field effect transistors. 3. Easy to fabricate an integrated sensor device.

Abstract: The present invention discloses an integrated ethanol gas sensor and fabrication thereof. The present invention utilities micro electro mechanical system (MEMS) technology and has a main sensing part in the form of a cantilever-bridge structure made of SiC thin film material arranged over a silicon substrate. The present invention integrates an SiC heater of comb or finger electrode shape and an SnO.sub.2 thin film gas sensing element applied over distinct portions on the same Si substrate together with Al2O3 and SnO2 thin films via a VLSI technology.

Abstract: A non-volatile ferroelectric memory device has been developed, in which the lead titanate (PbTiO.sub.3) thin film is deposited on a n/P.sup.+ Si substrate by rf magnetron sputtering as the gate oxide and Pt is embedded in the gate oxide as the floating gate. Additionally, associated with the rapid bulk channel structure with higher mobility, the developed memory device has the following features: (1) low write/erase voltage (.ltoreq.10 V); (2) fast access time (<160 ns); (3) easy to fabricate on VLSI memory device.

Abstract: A method of forming a contact in a thin film transistor with a gate electrode and an interconnect formed on a substrate, in an SRAM device comprises the following steps. Form a gate oxide layer over device. Form a split amorphous silicon layer over gate oxide layer. Form a cap layer over split amorphous silicon layer. Form a contact opening down to interconnect. Form contact metallization in opening on the surface of interconnect either as a blanket titanium layer followed by rapid thermal anneal to form a silicide and stripping unreacted titanium or by selective formation of a tungsten metal silicide in the opening. Strip cap layer from device. Form a second amorphous silicon layer on split silicon layer. Recrystallize silicon layers to form a polysilicon channel layer from amorphous silicon layers. Dope regions of polysilicon channel layer aside from a channel region above gate electrode.

Abstract: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact.

Abstract: A contact between a conductor and a substrate region in a MOSFET SRAM device is formed by a dielectric layer on the surface of a partially completed SRAM device with pass transistors and latch transistors with the dielectric layer being formed above those pass and latch transistors. A thin film transistor gate electrode and an interconnection line are formed on the upper surface of the dielectric layer. A gate oxide layer covers the gate electrode and the interconnection line. A polysilicon conductive layer which covers the gate oxide layer includes a channel region between a source region and a drain region which are formed on opposite sides of the channel region. There is a channel mask formed self-aligned with the channel region formed above the channel region as well as being above the gate electrode. The polysilicon conductive layer is doped aside from the channel mask thereby providing a source region and a drain region on opposite sides of the channel region.

Abstract: A method of manufacturing single-crystal silicon carbide/single-crystal silicon heterojunctions with negative differential resistance, by which one or more single-crystal silicon carbide/single-crystal silicon layer(s) with different types of dopants is/are formed on a silicon substrate, thereby forming new-type multiple negative differential resistance based on (a) single-crystal silicon carbide/single-crystal silicon heterojunction(s). The heterojunction(s) structure from top to bottom can be (1) Al/P--SiC/GCL/N--Si/Al; (2) Al/P--Si/GCL/P--SiC/GCL/N--Si/Al; and (3) Al/P--SiC/GCL/N--Si/GCL/P--SiC/GCL/N--Si/Al, wherein the GCL (Graded Reactant-gas Composition Ratio Layer) is a buffer layer formed between single-crystal silicon carbide layer and single-crystal silicon layer by gradually changing the composition of reaction gases. The structure and process of devices with negative differential resistance according to the invention are simpler than those of the prior art using Group III-V semiconductors.

Abstract: An integrated photoreceiver is provided. The photoreceiver includes a substrate, a metal-insulator-semiconductor switch (MISS) formed on a first portion of the substrate, and a photoreceiving structure formed on a second portion of the substrate for receiving a light signal and generating a current signal to trigger the MISS in response to said light signal.

Abstract: The present invention relates to a new process of the cantilever structure in the micro-electro-mechanical system (MEMS), and more particularly, to a process that could overcome the contamination problem on the undesired areas during the thin-film growth. Their advantages include not only to substitute the complex technique with sacrificial layer, but also to increase the yield for its simple structure and to deal the sub-micron microelectromechanical system technology for the mature stage on the wet-etching skill.

Abstract: This invention relates to the characterization of integrated circuit devices and more particularly to an improved method for monitoring for unacceptable kink behavior, in the threshold voltage characteristics of FET devices, that can be caused by a tendency for reduced gate oxide thickness and reduced substrate doping concentration, along the length of channel regions bounded by STI. This is achieved by comparing a pair of drain current versus gate voltage characteristics, as a function of two values of substrate voltage. Relative voltage shifts between the two curves are compared at a value of drain current that is well below the kink and at a value of drain current that is well above the kink. The quantitative degree of kink behavior is determined by how much greater the voltage shift, corresponding to the value of drain current well above the kink, exceeds the voltage shift, corresponding to the value of drain current well below the kink.

Abstract: A contact process interconnects poly-crystal silicon layer, and more particularly, this process dramatically decreases the voltage drop within a poly-crystal silicon layer. The advantages of the process include not only improvement in the interface quality of Poly-Si/SiO2 to decrease the junction damage but also do not increase its process complexity and its mask number during the fabrication of poly-crystal silicon thin-film SRAM to meet high integration requirement in VLSI.

Abstract: A method of forming a contact between a conductor and a substrate region in a MOSFET SRAM starts with forming a dielectric layer on the surface of a partially completed SRAM device with pass and latch transistors covering the transistors. Then, form a thin film gate electrode and an interconnect on the dielectric layer with a gate oxide layer covering the gate electrode and the interconnect; cover the gate oxide layer with a poly conductive layer. Then form a silicon oxide layer over the poly conductive layer and pattern the silicon oxide layer to form a silicon oxide channel mask over the poly conductive layer which is used to pattern the silicon oxide layer into a channel mask over the gate electrode. The channel mask is used for patterning the implanting of dopant into the poly conductive layer aside from the channel mask to form a source region, a drain region and an interconnect in the poly conductive layer.

Abstract: An infrared optical field effect transistor has been developed using a thin film of Lead Titanate (PbTiO.sub.3) deposited on a n/p.sup.+ Si substrate by RF magnetron sputtering. This transistor possesses excellent pyroelectric properties and can, therefore, be operated even at room temperature. The infrared optical field effect transistor has the following features associated with rapid bulk channel structure and higher mobility:1. Can be operated at room temperature, unlike quantum type IR sensors which can only operate at very low temperature (-100.degree. C..about.-200.degree. C.), which results in higher costs.2. High speed response with only 2.3 .mu.s of rise time. This is much faster than other types of thermal infrared optical field effect transistors.3. Easy to fabricate an integrated sensor device.

Abstract: An amorphous silicon color detector comprising a structure composed of a transparent conductive oxide film (TCO) layer/an a-Si:H layer/a metal layer, of which the a-Si:H layer is an amorphous silicone layer having a thickness greater than 1 .mu.m, and the metal layer is made of a metals selected from the metal group consisting of Cr, Au, Pd, Al, Pt, Mo, Ag or Ti. A depletion region of the color detector is re-arranged in position and in content thereof according to the absorbencies to different color lights in different bias voltages to achieve the purpose of detecting different color light. An amorphous silicone color image sensor comprises a plurality of the color detectors arranged in linear array incorporated with a scanning device, a processor and an A/D converter to process the signals obtained from scanning. The amorphous silicone color image sensor is especially used in a scanning machine or a fax machine. A manufacture process of the amorphous silicon color detector is also disclosed.

Abstract: A method of manufacturing a light converter with an LED and an amorphous-silicon pin heterojunction diode includes steps of a) preparing an LED structure on one side of a substrate as a light-emitting unit; b) forming a buffer layer on the other side of the substrate; and c) depositing a pin (positive type/intrinsic type/negative type) diode on the buffer layer as a light-absorbing unit this blue/red light converter, and the value of rise time obtained under 1 k.OMEGA. is 112.5 .mu.sec. The present invention desirably lower the cost, simplify the preparation process, and avoids degrading features of a light converting unit by over-heating during the process of preparing the pin diode.

Abstract: A method of manufacturing a light converter with an LED and an amorphous-silicon pin heterojunction diode includes steps of a) preparing an LED structure on one side of a substrate as a light-emitting unit; b) forming a buffer layer on the other side of the substrate; and c) depositing a pin (positive type/intrinsic type/negative type) diode on the buffer layer as a light-absorbing unit this blue/red light converter, and the value of rise time obtained under 1 kf.OMEGA. is 112.5 .mu.sec. The present invention desirably lower the cost, simplify the preparation process, and avoids degrading features of a light converting unit by over-heating during the process of preparing the pin diode.

Abstract: A color filter comprising a transparent substrate and two or more multilayer films of amorphous silicon materials deposited on said substrate, each film being different, each layer of said two or more multi-layer films having a thickness less than the wavelength of the visible light and at least three layers of said two or more multi-layer films of amorphous silicon materials in an alternate arrangement wherein the amorphous silicon materials are selected from a-SiOx and a-SiNx is described. A method of preparing the color filter comprising depositing on the substrate by PECVD method two or more multilayer films is also described. The color filters prepared by PECVD method have a more compact texture and a better environmental resistant. The PECVD method for the preparation of the filters is more efficient than conventional methods.

Abstract: An amorphous silicon color detector comprising a structure composed of a transparent conductive oxide film (TCO) layer/an a-Si:H layer/a metal layer, of which the a-Si:H layer is an amorphous silicone layer having a thickness greater than 1 .mu.m, and the metal layer is made of a metals selected from the metal group consisting of Cr, Au, Pd, Al, Pt, Mo, Ag or Ti. A depletion region of the color-detector is re-arranged in position and in content thereof according to the absorbencies to different color lights in different bias voltages to achieve the purpose of detecting different color light. An amorphous silicone color image sensor comprises a plurality of the color detectors arranged in linear array incorporated with a scanning device, a processor and an A/D converter to process the signals obtained from scanning. The amorphous silicone color image sensor is especially used in a scanning machine or a fax machine. A manufacture process of the amorphous silicon color detector is also disclosed.