Abstract: A printed circuit board (PCB) including an embedded electronic component is provided. The printed circuit board includes a core having a cavity, an electronic component inserted into the cavity having a rough surface formed on surfaces of external electrodes provided on both lateral portions thereof, a low rough surface being formed in a portion of the rough surfaces, insulating layers laminated on upper and lower portions of the core and bonded to an outer circumferential surface of the electronic component insertedly positioned in the cavity, and an external circuit pattern provided on the insulating layers.

Abstract: Disclosed herein is a printed circuit board (PCB) including an embedded electronic component, including: a core having a cavity; an electronic component inserted into the cavity having a rough surface formed on surfaces of external electrodes provided on both lateral portions thereof, a low rough surface being formed in a portion of the rough surfaces; insulating layers laminated on upper and lower portions of the core and bonded to an outer circumferential surface of the electronic component insertedly positioned in the cavity; and an external circuit pattern provided on the insulating layers.

Abstract: Disclosed herein is a printed circuit board (PCB) including an embedded electronic component, including: a core having a cavity; an electronic component inserted into the cavity having a rough surface formed on surfaces of external electrodes provided on both lateral portions thereof, a low rough surface being formed in a portion of the rough surfaces; insulating layers laminated on upper and lower portions of the core and bonded to an outer circumferential surface of the electronic component insertedly positioned in the cavity; and an external circuit pattern provided on the insulating layers.

Abstract: A circuit board includes an inorganic material insulating layer, a first circuit pattern layer formed on a surface of the inorganic material insulating layer, a first build-up insulating layer formed on the inorganic material insulating layer and formed of an organic material, and a second circuit pattern layer formed on a surface of the first build-up insulating layer.

Abstract: Disclosed herein are a printed circuit board including an electronic component embedded therein and a method for manufacturing the same. The printed circuit board including an electronic component embedded therein includes: a core formed with a cavity which is formed of a through hole and has a side wall formed with an inclined surface having a top and bottom symmetrically formed based on a central portion thereof; an electronic component embedded in the cavity; insulating layers stacked on upper and lower portions of the core including the electronic component; and external circuit layers formed on the insulating layers.

Abstract: Disclosed herein are a printed circuit board having an embedded electronic device and a method of manufacturing the same. According to a preferred embodiment of the present invention, the printed circuit board having an embedded electronic device includes: a core substrate having circuit layers formed on both surfaces thereof; a taper-shaped cavity formed on the core substrate; and an electronic device embedded in the cavity.

Abstract: Disclosed herein is a multilayered substrate including: a second insulating layer having a fine pattern layer formed on an upper surface thereof; and a third insulating layer having a circuit pattern layer formed on an upper surface thereof and formed of a material different from the second insulating layer, the circuit pattern layer having a pattern pitch larger than that of the fine pattern layer, thereby making it possible to solve a warpage problem and perform refinement and improvement in a degree of integration of an inner wiring.

Abstract: The present invention relates to an electronic component embedded substrate including: a first insulating layer including a cavity; an electronic component inserted in the cavity; a first metal pattern formed on a lower surface of the first insulating layer to mount the electronic component thereon and including at least one guide hole for exposing a portion of the external electrode; a second insulating layer formed on the lower surface of the first insulating layer to cover the first metal pattern; a first circuit pattern formed on a lower surface of the second insulating layer; and a first via for electrically connecting the first external electrode exposed through the guide hole and the first circuit pattern, and can improve electrical connectivity between the external electrode and the via even when the size of the external electrode of the electronic component is reduced than before.

Abstract: A substrate embedding a passive element includes a first conductor pattern layer disposed on a lower surface thereof and a second conductor pattern layer disposed on an upper surface thereof; a first via electrically connecting between the passive element and the first conductor pattern layer; and a second via electrically connecting between the passive element and the second conductor pattern layer, in which a volume of the first via is larger than that of the second via.

Abstract: A circuit board includes an inorganic material insulating layer, a first circuit pattern layer formed on a surface of the inorganic material insulating layer, a first build-up insulating layer formed on the inorganic material insulating layer and formed of an organic material, and a second circuit pattern layer formed on a surface of the first build-up insulating layer.

Abstract: The present invention relates to a multilayer ceramic capacitor and a printed circuit board including the same that can minimize thickness deviations of an external electrode and a multilayer ceramic. A multilayer ceramic capacitor according to an embodiment of the present invention includes a multilayer ceramic and external electrodes formed on both sides of the multilayer ceramic, wherein |Tmax?Tmin| may be less than 10 ?m, and |CTmax?CTmin| may be less than 20 ?m. (Here, Tmax is a maximum thickness of the external electrodes in a via processing area, Tmin is a minimum thickness of the external electrodes in the via processing area, CTmax is a maximum thickness of the multilayer ceramic capacitor in the via processing area, and CTmin is a minimum thickness of the multilayer ceramic capacitor in the via processing area.

Abstract: A substrate having an electronic component embedded therein includes a first insulating layer including a cavity and including first and second circuit patterns provided on upper and lower surfaces thereof, respectively; the electronic component at least partially inserted into the cavity and including an external electrode; a plurality of build-up insulating layers stacked on or beneath the first insulating layer; upper and lower circuit patterns formed on the build-up insulating layers, respectively; and a plurality of vias connecting the external electrode, the upper circuit pattern, the first circuit pattern, the second circuit pattern, and the lower circuit pattern.

Abstract: A multilayered substrate and a method of manufacturing the same. The multilayered substrate includes a plurality of wiring layers and reinforcing layers disposed at the outermost portions of both surfaces of the multilayered substrate, respectively, in order to decrease warpage of the multilayered substrate and has wiring patterns optimized depending on a scheme in which external electrodes are formed on an electronic component.

Abstract: Disclosed herein is a method for manufacturing a semiconductor package. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip.

Abstract: Disclosed herein is a method for manufacturing a semiconductor package. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip.

Abstract: The present invention relates to a passive device embedded in a substrate, which includes a laminate formed by alternately laminating a plurality of internal electrodes and dielectric layers; a first external electrode covering one side surface of the laminate and having a first upper cover region, which covers a part of an upper portion of the laminate, and a first lower cover region, which covers a part of a lower portion of the laminate and is smaller than the first upper cover region; and a second external electrode covering the other side surface of the laminate and having a second lower cover region, which covers a part of the lower portion of the laminate, and a second upper cover region, which covers a part of the upper portion of the laminate and is smaller than the second lower cover region, and the substrate.

Abstract: A multilayered substrate includes an insulating layer or core comprised of a glass material and having a light transmittance of about 50% or less; circuit pattern layers or parts respectively formed on the surfaces of the insulating layer or core; and a build-up part covering a surface of the insulating layer or core and one of the circuit pattern layers

Abstract: Disclosed herein is a method for manufacturing a semiconductor package. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip.

Abstract: Disclosed herein is a printed circuit board (PCB) including a glass core for maintaining sufficient rigidity while maintaining a thin thickness to minimize warpage. The PCB includes a glass core having upper and lower surfaces in which pattern formation grooves and through via holes are formed, a plating layer filled in the pattern formation groves and the through via holes, insulating layers stacked on the upper and lower surfaces of the glass core, and solder resist layers formed on the insulating layers via coating.

Abstract: Disclosed herein are a printed circuit board having an embedded electronic device and a method of manufacturing the same. According to a preferred embodiment of the present invention, the printed circuit board having an embedded electronic device includes: a core substrate having circuit layers formed on both surfaces thereof; a taper-shaped cavity formed on the core substrate; and an electronic device embedded in the cavity.