Abstract: Methods of amplifying and determining a target nucleotide sequence are provided. The method of amplifying the target nucleotide sequence includes the following steps. A first adaptor and a second adaptor are linked to two ends of a double-stranded nucleic acid molecule with a target nucleotide sequence respectively to form a nucleic acid template, in which the first adaptor includes a Y-form adaptor or a hairpin adaptor and the second adaptor is a hairpin adaptor. Then, a PCR amplification cycle is performed on the nucleic acid template to obtain a PCR amplicon of the target nucleotide sequence.

Abstract: A strap tensioner includes a frame, a bridge bar, a stopper, a winding shaft, a gear assembly, a crank and an observation hole. The frame has two sidewalls. The bridge bar is fixed between the two sidewalls. The stopper is of an L-shape and extends from one of the sidewalls. The gear assembly is mounted on the other sidewall and has a worm and a worm gear. The worm gear is axially connected to the winding shaft. The worm is provided with a drive shaft. The crank includes a stem connected to the drive shaft, an arm pivotedly connected to the stem and being capable of being either expanded along the stem or folded over the stem, and a handle on the arm. The observation hole is formed in the sidewall. The handle is blocked by the stopper when the arm is folded over the stem.

Abstract: An integrated circuit includes a first circuit having a loopback path electrically coupled to an inverter and a test circuit having a controller and a counter. The test circuit is electrically coupled to the first circuit, and the controller is configured to select the loopback path. The first circuit is configured to receive a first voltage signal and to generate an oscillating signal from the received first voltage signal. The first voltage signal is either a substantially low logic level signal or a substantially high logic level signal. The counter is configured to count oscillations of the oscillating signal.

Abstract: A strap tensioner includes a frame, a bridge bar, a stopper, a winding shaft, a gear assembly, a crank and an observation hole. The frame has two sidewalls. The bridge bar is fixed between the two sidewalls. The stopper is of an L-shape and extends from one of the sidewalls. The gear assembly is mounted on the other sidewall and has a worm and a worm gear. The worm gear is axially connected to the winding shaft. The worm is provided with a drive shaft. The crank includes a stem connected to the drive shaft, an arm pivotedly connected to the stem and being capable of being either expanded along the stem or folded over the stem, and a handle on the arm. The observation hole is formed in the sidewall. The handle is blocked by the stopper when the arm is folded over the stem.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a first metal layer over a semiconductor substrate, and forming a first layer over the first metal layer. The first layer and first metal layer are etched to expose a sidewall of the first layer and a sidewall of the first metal layer, wherein the etching disburses a portion of the first metal layer to create an accumulation of material on at least one of the sidewall of the first layer or the sidewall of the first metal layer. At least some of the accumulation is etched away using an etchant comprising fluorine.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a first metal layer over a semiconductor substrate, and forming a first layer over the first metal layer. The first layer and first metal layer are etched to expose a sidewall of the first layer and a sidewall of the first metal layer, wherein the etching disburses a portion of the first metal layer to create an accumulation of material on at least one of the sidewall of the first layer or the sidewall of the first metal layer. At least some of the accumulation is etched away using an etchant comprising fluorine.

Abstract: An integrated circuit includes a first circuit having a loopback path electrically coupled to an inverter and a test circuit having a controller and a counter. The test circuit is electrically coupled to the first circuit, and the controller is configured to select the loopback path. The first circuit is configured to receive a first voltage signal and to generate an oscillating signal from the received first voltage signal. The first voltage signal is either a substantially low logic level signal or a substantially high logic level signal. The counter is configured to count oscillations of the oscillating signal.

Abstract: An integrated circuit for testing a circuit includes a controller configured to select a loopback path of the circuit. The circuit includes a data path and an inverter, and each is electrically coupled to the selected loopback path. The integrated circuit includes a counter electrically coupled to the selected loopback path. The circuit is configured to receive a first voltage signal that is either a substantially low logic level signal or a substantially high logic level signal. The circuit is configured to generate an oscillating signal from the first voltage signal, and the counter is configured to count oscillations of the oscillating signal.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a first metal layer over a semiconductor substrate, and forming a first layer over the first metal layer. The first layer and first metal layer are etched to expose a sidewall of the first layer and a sidewall of the first metal layer, wherein the etching disburses a portion of the first metal layer to create an accumulation of material on at least one of the sidewall of the first layer or the sidewall of the first metal layer. At least some of the accumulation is etched away using an etchant comprising fluorine.

Abstract: The system includes a body having a first side wall, a second side wall and a rod therebetween; a main shaft set, pivoted between the first and second side walls, including a main shaft, an end of the main shaft being disposed a ratchet and a first bevel gear; a transmission shaft, pivoted outside the second side wall of the body, a second bevel gear being axially connected around the transmission shaft, the second bevel gear engaging with the first bevel gear, and a gear ratio of the first and second bevel gears being 2:1; a handle set axially connected to the transmission shaft; and a pawl set pivoted on the second side wall of the body to fit into a notch of the ratchet to prevent the main shaft set from reversing.

Abstract: An integrated circuit for testing a circuit includes a controller configured to select a loopback path of the circuit. The circuit includes a data path and an inverter, and each is electrically coupled to the selected loopback path. The integrated circuit includes a counter electrically coupled to the selected loopback path. The circuit is configured to receive a first voltage signal that is either a substantially low logic level signal or a substantially high logic level signal. The circuit is configured to generate an oscillating signal from the first voltage signal, and the counter is configured to count oscillations of the oscillating signal.

Abstract: Some embodiments of the present disclosure provide a method including turning on a noise-measuring system for a device under test (DUT) with the DUT turned off; measuring a first phase noise caused by the noise-measuring system; turning on the DUT; measuring a second phase noise caused by the noise-measuring system and the DUT; and subtracting the first phase noise from the second phase noise to obtain a third phase noise caused by the DUT.

Abstract: An integrated circuit includes a first circuit and a test circuit. The test circuit is configured to test the timing of a first circuit. The first circuit includes a plurality of flip-flops and a plurality of data paths. Each data path of the plurality of data paths is connected to one or more of the plurality of flip-flops. The test circuit includes a plurality of loopback paths, a controller, a multiplexer connected to the plurality of loopback paths and a counter connected to the multiplexer. The controller is configured to select a path from the plurality of loopback paths and the plurality of data paths. The multiplexer is configured to selectively output a first signal including an oscillation frequency. The first signal is applied to the selected path and the counter is configured to measure the oscillation frequency of the first signal.

Abstract: A strap tightener for securing cargo is disclosed. The tightener includes a base frame and a handling frame, which pivotally connect to form a vee structure. The base frame is connected to the handling frame by inserting a pivot into pivot hole thereof. Each of two ends of the pivot is ringed with a protection loop and a ratchet wheel. The protection loop is composed of a flange for being blockedly fixed on the pivot hole and a sleeve for penetrating into the pivot hole. The sleeve can protect the pivot hole to prevent it from being directly pressed by the pivot.

Abstract: A calibration procedure that uses direct measurement of digital phase error performance for low cost calibration of all-digital phase locked loop (ADPLL)/digitally-controlled oscillator (DCO) is described. Direct measurement of digital phase error, or difference in digital phase error, is used to adjust the operating point of the DCO and thereby determine the operating point that provides the optimal phase noise of the output signal. Calibration may be performed at any time so that changes in external factors such as process, voltage and temperature (PVT) may be incorporated into the setting of the operating point of the DCO.

Abstract: A calibration procedure that uses direct measurement of digital phase error performance for low cost calibration of all-digital phase locked loop (ADPLL)/digitally-controlled oscillator (DCO) is described. Direct measurement of digital phase error, or difference in digital phase error, is used to adjust the operating point of the DCO and thereby determine the operating point that provides the optimal phase noise of the output signal. Calibration may be performed at any time so that changes in external factors such as process, voltage and temperature (PVT) may be incorporated into the setting of the operating point of the DCO.

Abstract: The chain binder includes a main tube and two links separately screwed to the main tube. A U-shaped seat has two parallel side plates and a hollow portion and is pivoted by the main tube. A gear is fastened to the main tube and received in the hollow portion. A claw with two pairs of claw teeth and handle teeth is rotatably disposed between the two side plates. The claw and the gear compose a ratchet mechanism. A claw positioner is disposed on seat and is selectably inserted into a positioning hole of the claw. A lever set is rotatably and elastically connected to a U-shaped frame attached on the seat. The lever set will be rotatable when it is pulled out.

Abstract: A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation.

Abstract: A device includes a delay line, a first readout circuit electrically connected to the delay line, a second readout circuit electrically connected to the delay line, and a phase interpolator electrically connected to the second readout circuit.

Abstract: An image sensor includes a photosensing element for receiving infrared (IR) radiation and detecting the IR radiation and generating an electrical signal indicative of the IR radiation. A redistribution layer (RDL) is disposed under the photosensing element, the RDL comprising pattern of conductors for receiving the electrical signal. An IR reflection layer, an IR absorption layer or an isolation layer is disposed between the photosensing element and the RDL. The IR reflection layer, IR absorption layer or isolation layer provides a barrier to IR radiation such that the IR radiation does not impinge upon the RDL. As a result, a ghost image of the RDL is not generated, resulting in reduced noise and improved sensitivity and performance of the image sensor.