Patents by Inventor Yelehanka Ramachandramurthy Pradeep
Yelehanka Ramachandramurthy Pradeep has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9633882Abstract: Methods of producing integrated circuits with interposers and integrated circuits produced from such methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a base layer overlying a substrate, and forming an alignment mark overlying the base layer. A first layer is formed overlying the base layer and the alignment mark, and the first layer has a first layer thickness. A second layer is formed overlying the first layer, where the second layer has a second layer thickness and where a combined thickness of the first and second layer thicknesses is from about 2 to about 50 micrometers. A second component is formed from the second layer.Type: GrantFiled: September 29, 2015Date of Patent: April 25, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Ying Yu, Jianbo Sun, Derui Yin, Yelehanka Ramachandramurthy Pradeep, Rakesh Kumar
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Publication number: 20170092523Abstract: Methods of producing integrated circuits with interposers and integrated circuits produced from such methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a base layer overlying a substrate, and forming an alignment mark overlying the base layer. A first layer is formed overlying the base layer and the alignment mark, and the first layer has a first layer thickness. A second layer is formed overlying the first layer, where the second layer has a second layer thickness and where a combined thickness of the first and second layer thicknesses is from about 2 to about 50 micrometers. A second component is formed from the second layer.Type: ApplicationFiled: September 29, 2015Publication date: March 30, 2017Inventors: Ying Yu, Jianbo Sun, Derui Yin, Yelehanka Ramachandramurthy Pradeep, Rakesh Kumar
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Patent number: 8293545Abstract: Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.Type: GrantFiled: October 29, 2007Date of Patent: October 23, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Hai Cong, Yan Shan Li, Chun Hui Low, Yelehanka Ramachandramurthy Pradeep, Liang Choo Hsia
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Publication number: 20090108257Abstract: Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.Type: ApplicationFiled: October 29, 2007Publication date: April 30, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Hai Cong, Yan San Li, Chun Hui Low, Yelehanka Ramachandramurthy Pradeep, Liang Choo Hsia
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Publication number: 20050136573Abstract: A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop.Type: ApplicationFiled: January 28, 2005Publication date: June 23, 2005Inventors: Purakh Rajverma, Sanford Chu, Lap Chan, Yelehanka Ramachandramurthy Pradeep, Kai Shao, Jia Zheng
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Publication number: 20050130402Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.Type: ApplicationFiled: January 27, 2005Publication date: June 16, 2005Inventors: Yelehanka Ramachandramurthy Pradeep, Tong Chen, Zhi Han, Zhen Zheng, Kelvin Ong, Tian Gu, Syn Cheah
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Publication number: 20050124131Abstract: A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.Type: ApplicationFiled: January 13, 2005Publication date: June 9, 2005Inventors: Chit Hweing, Lap Chan, Purakh Verma, Yelehanka Ramachandramurthy Pradeep, Sanford Chu
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Publication number: 20050059216Abstract: A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop.Type: ApplicationFiled: September 17, 2003Publication date: March 17, 2005Inventors: Purakh Verma, Sanford Chu, Lap Chan, Yelehanka Ramachandramurthy Pradeep, Kai Shao, Jia Zheng
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Patent number: 6852605Abstract: A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.Type: GrantFiled: May 1, 2003Date of Patent: February 8, 2005Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chit Hwei Ng, Lap Chan, Purakh Verma, Yelehanka Ramachandramurthy Pradeep, Sanford Chu
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Patent number: 6821904Abstract: In accordance with the objectives of the invention a new method is provided for the creation of layers of gate oxide having an unequal thickness. Active surface regions are defined over the surface of a substrate, a thick layer of gate oxide is grown over the active surface. A selective etch is applied to the thick layer of gate oxide, selectively reducing the thickness of the thick layer of gate oxide to the required thickness of a thin layer of gate oxide. The layer of thick gate oxide is blocked from exposure. N2 atoms are implanted into the exposed surface of the thin layer of oxide, rapid thermal processing is performed and the blocking mask is removed from the surface of the thick layer of gate oxide. A high concentration of nitride has now been provided in the thin layer of gate oxide.Type: GrantFiled: July 30, 2002Date of Patent: November 23, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yelehanka Ramachandramurthy Pradeep, Sanford Chu, Chit Hwei Ng, Jia Zhen Zheng, Purakh Verma
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Publication number: 20040217440Abstract: A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.Type: ApplicationFiled: May 1, 2003Publication date: November 4, 2004Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Chit Hwei Ng, Lap Chan, Purakh Verma, Yelehanka Ramachandramurthy Pradeep, Sanford Chu
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Patent number: 6791083Abstract: An apparatus for preventing distortion to critical dimension line images formed by a SEM under the influence of external electro-magnetic emissions generating by neighboring manufacturing equipment. The external emission causes a high three sigma A/C component. The correcting apparatus includes an external shielding coil mounted to the column housing of the SEM. A control electro-emission driver is mounted to the external shielding coil in which a variable voltage divider having a transformer with a variable resistor. The variable resistor is adjusted varying the amplitude of the sine wave of the A/C signal thus controlling the electro-emission driver while reducing the effects of the three sigma A/C component.Type: GrantFiled: July 29, 2002Date of Patent: September 14, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kevin Chan Ee Peng, Yelehanka Ramachandramurthy Pradeep, Chua Thow Phock
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Patent number: 6726545Abstract: A linear polishing apparatus for polishing a semiconductor substrate including a novel polishing belt arrangement with at least two polishing belts forming a continuous loop. Each belt having an outside polishing surface and an inside smooth surface. The belts are spaced alongside each other sharing a common axis at each end. The belts are looped around a pair of rollers making up a driver roller at one end and a driven roller at the other end. A platen member interposes each belt and is placed between the pairs of rollers. The platen provides a polishing plane and supporting surface for the polishing belts. The polishing plane includes a plurality of holes communicating with an elongated plenum chamber underlying the plane. The chamber supplies a compressed gas to impart an upward pressure against the polishing belts. The driver rollers are coupled to separate motors to independently drive and control at least said two of the polishing belts.Type: GrantFiled: April 26, 2002Date of Patent: April 27, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Subramanian Balakumar, Chen Feng, Victor Lim, Paul Proctor, Mukhopadhyay Madhusudan, Chivukula Subrahmanyam, Yelehanka Ramachandramurthy Pradeep
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Method of forming a surface coating layer within an opening within a body by atomic layer deposition
Patent number: 6716693Abstract: An improved new process for fabricating multilevel interconnected vertical channels and horizontal channels or tunnels. The method has broad applications in semiconductors, for copper interconnects and inductors, as well as, in the field of bio-sensors for mini- or micro-columns in gas or liquid separation, gas/liquid chromatography, and in capillary separation techniques. In addition, special techniques are described to deposit by atomic layer deposition, ALD, a copper barrier layer and seed layer for electroless copper plating, filling trench and channel or tunnel openings in a type of damascene process, to form copper interconnects and inductors.Type: GrantFiled: March 27, 2003Date of Patent: April 6, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Lap Chan, Sanford Chu, Chit Hwei Ng, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng -
Patent number: 6709934Abstract: A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.Type: GrantFiled: July 16, 2002Date of Patent: March 23, 2004Assignee: Chartered Semiconductor Manufacturing LtdInventors: James Yong Meng Lee, Ying Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan
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Publication number: 20040023506Abstract: In accordance with the objectives of the invention a new method is provided for the creation of layers of gate oxide having an unequal thickness. Active surface regions are defined over the surface of a substrate, a thick layer of gate oxide is grown over the active surface. A selective etch is applied to the thick layer of gate oxide, selectively reducing the thickness of the thick layer of gate oxide to the required thickness of a thin layer of gate oxide. The layer of thick gate oxide is blocked from exposure. N2 atoms are implanted into the exposed surface of the thin layer of oxide, rapid thermal processing is performed and the blocking mask is removed from the surface of the thick layer of gate oxide. A high concentration of nitride has now been provided in the thin layer of gate oxide.Type: ApplicationFiled: July 30, 2002Publication date: February 5, 2004Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Yelehanka Ramachandramurthy Pradeep, Sanford Chu, Chit Hwei Ng, Jia Zhen Zheng, Purakh Verma
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Publication number: 20040016881Abstract: An apparatus for preventing distortion to critical dimension line images formed by a SEM under the influence of external electromagnetic emissions generated by neighboring manufacturing equipment. The external emission causes a high three sigma A/C component. The correcting apparatus includes an external shielding coil mounted to the column housing of the SEM. A control electro-emission driver is mounted to the external shielding coil in which a variable voltage divider having a transformer with a variable resistor. The variable resistor is adjusted varying the amplitude of the sine wave of the A/C signal thus controlling the electro-emission driver while reducing the effects of the three sigma A/C component.Type: ApplicationFiled: July 29, 2002Publication date: January 29, 2004Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Kevin Chan Ee Peng, Yelehanka Ramachandramurthy Pradeep, Chua Thow Phock
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Publication number: 20040004054Abstract: A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a a layer of choice.Type: ApplicationFiled: July 5, 2002Publication date: January 8, 2004Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Yelehanka Ramachandramurthy Pradeep, Sanford Chu, Chit Hwei Ng, Jia Zhen Zheng, Purakh Verma
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Patent number: 6660642Abstract: A novel method to remove residual toxic gases trapped by a polymerizing process by an inert ion sputter is described. A masking layer is formed overlying a semiconductor substrate. An opening is etched through the masking layer into the semiconductor substrate whereby a polymer forms on sidewalls of the opening and whereby residual toxic gas reactants from gases used in the etching step are adsorbed by the polymer. Thereafter, the polymer is sputtered with non-reactive ions whereby the residual toxic gas reactants are desorbed from the polymer to complete removal of residual toxic gas reactants in the fabrication of an integrated circuit device.Type: GrantFiled: July 25, 2001Date of Patent: December 9, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Zou Zheng, Zhou Mei Sheng, Yelehanka Ramachandramurthy Pradeep, Paul Proctor
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Publication number: 20030203710Abstract: A linear polishing apparatus for polishing a semiconductor substrate including a novel polishing belt arrangement with at least two polishing belts forming a continuous loop. Each belt having an outside polishing surface and an inside smooth surface The belts are spaced alongside each other sharing a common axis at each end. The belts are looped around a pair of rollers making up a driver roller at one end and a driven roller at the other end. A platen member interposes each belt and is placed between the pairs of rollers. The platen provides a polishing plane and supporting surface for the polishing belts. The polishing plane includes a plurality of holes communicating with an elongated plenum chamber underlying the plane. The chamber supplies a compressed gas to impart an upward pressure against the polishing belts. The driver rollers are coupled to separate motors to independently drive and control at least said two of the polishing belts.Type: ApplicationFiled: April 26, 2002Publication date: October 30, 2003Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Subramanian Balakumar, Chen Feng, Victor Seng-Keong Lim, Paul Proctor, Mukhopadhyay Madhusudan, Chivukula Subrahmanyam, Yelehanka Ramachandramurthy Pradeep