Abstract: A method for anisotropically etching a partially manufactured semiconductor structure, more specifically, a stacked FET gate structure containing a bottom anti-reflective coating (Barc) layer is described. The structure is covered with a photoresist layer which is patterned to defines the gate region. The processing chemistry is predominantly carbon tetrafluoride, (CF4) with the inclusion of chlorine (Cl2) where fluorine (F) is generated in the plasma as the etchant for the structure. During processing, the wafer is cooled with helium (He) that lowers the wafer temperature and promotes sidewall deposition from the fluorine species which acts as a passivation layer producing a anisotropic or vertical etch profile. The process reduces etch time and results in very repeatable end point control of the Bark etch and poly cap etch improving the control of the structure critical dimensions and improving process throughput. The reduction in the use of fluorine based species reduces any potential environmental impact.

Abstract: A method for forming an L-shaped spacer using a sacrificial organic top coating. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. In the preferred embodiment, the dielectric spacer layer comprises a silicon nitride layer or a silicon oxynitride layer. A sacrificial organic layer is formed on the dielectric spacer layer. The sacrificial organic layer and the dielectric spacer layer are anisotropically etched to form spacers comprising a triangle-shaped sacrificial organic structure and an L-shaped dielectric spacer. The triangle-shaped sacrificial organic structure is removed leaving an L-shaped dielectric spacer.

Abstract: A method for a T-gate and salicide process that allows narrow bottom gate widths below 0.25 &mgr;m and wide top gate widths to allow silicide gate contacts on the top of the T-gate. A dummy gate composed of an insulating material is formed over the substrate. Then we form LDD regions adjacent to the dummy gate preferably by ion implanting f (I/I) impurity ions into the substrate using the dummy gate as a mask. A pad oxide layer and dielectric layer are formed over the substrate surface. The dielectric layer over the dummy gate is removed preferably by a CMP process. We then remove the dummy gate to form a gate opening exposing the substrate surface. A gate dielectric layer is formed over the substrate surface in the gate opening. We form a polysilicon layer over the dielectric layer and the substrate surface in the gate opening. The polysilicon layer is patterned to form a T-gate. The dielectric layer is removed. We forming source/drain (S/D) regions adjacent to the T-gate by an Ion implant process.

Abstract: A new method of fabricating shallow trench isolations has been achieved. A silicon dioxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the silicon dioxide layer. The silicon nitride layer is patterned to expose the semiconductor substrate where shallow trench isolations are planned. Ions are implanted into the exposed semiconductor substrate. The implanting damages any passive surface materials overlying the semiconductor substrate. The exposed semiconductor substrate is etched down to form trenches. The damaged passive surface materials are removed during the etching down to thereby prevent trench cone formation. A trench filling layer is deposited to fill the trenches. The trench filling layer is polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.

Abstract: A method of etching silicon nitride spacers beside a gate structure comprising: providing a gate electrode over a gate oxide layer on a substrate. A liner oxide layer is provided over the substrate and the gate electrode. A silicon nitride layer is provided over the liner oxide layer. The invention's nitride etch recipe is performed in a plasma etcher to anisotropically etch the silicon nitride layer to create spacers. The nitride etch recipe comprises a main etch step and an over etch step. The main etch step comprises the following conditions: a Cl2 flow between 35 and 55 molar %, a He flow between 35 and 55 molar %, a backside He pressure between 4 and 10 torr; and a HBr flow between 7.5 and 12.5 molar %; a pressure between 400 to 900 mTorr; at a power between 300 and 600 Watts. The etch recipe provides a spacer width to nitride layer thickness ratio of about 1:1 and does not pit the Si substrate surface.

Abstract: A process for forming salicided CMOS devices, and non-salicide CMOS devices, on the same semiconductor substrate, using only one silicon nitride layer to provide a component for a composite spacer on the sides of the salicided CMOS devices, and to provide a blocking shape during metal silicide formation, for the non-salicided CMOS devices, has been developed. The process features the use of a disposable organic spacer, on the sides of polysilicon gate structures, used to define the heavily doped source/drain regions, for all CMOS devices. A silicon nitride layer, obtained via LPCVD procedures, at a temperature between 800 to 900° C., is then deposited and patterned to provide the needed spacer, on the sides of the CMOS devices experiencing the salicide process, while the same silicon nitride layer is used to provide the blocking shape needed to prevent metal suicide formation for the non-salicided CMOS devices.

Abstract: A new method of forming silicon nitride sidewall spacers has been achieved. This method is used to fabricate tapered, L-shaped spacer profiles using a two-step etching process that can be performed insitu. In accordance with the objects of this invention, a new method of forming silicon nitride sidewall spacers has been achieved. An isolation region is provided overlying a semiconductor substrate. Conductive traces are provided overlying the insulator layer. A liner oxide layer is deposited overlying the conductive traces and the insulator layer. A silicon nitride layer is deposited overlying the liner oxide layer. The silicon nitride layer is anisotropically etched down to reduce the vertical thickness of the silicon nitride layer while not exposing the underlying liner oxide layer. The silicon nitride layer is etched through to form silicon nitride sidewall spacers adjacent to the conductive traces.

Abstract: A new apparatus is provided that allows for uniform polishing of semiconductor surfaces. The single polishing pad of conventional CMP methods is divided into a split pad, the split pad allows for separate adjustments of CMP control parameters across the surface of the wafer. These adjustments can extend from the center of the wafer to its perimeter (along the radius of the wafer) thereby allowing for the elimination of conventional problems of non-uniformity of polishing between the center of the surface that is polished and the perimeter of the surface that is polished.

Abstract: A new method of forming metal interconnects with air gaps between adjacent interconnects in the manufacture of an integrated circuit device is achieved. A semiconductor substrate is provided. The metal interconnects are formed overlying the semiconductor substrate. A silicon nitride liner layer is deposited. A gap filling oxide layer is deposited to fill gaps between adjacent metal interconnects. The gap filling oxide layer is polished down to the silicon nitride liner layer. A silicon nitride thin layer is deposited. The silicon nitride thin layer is patterned using an oversized, reverse mask of the metal interconnects. The patterning of the silicon nitride thin layer creates openings to thereby expose a portion of the gap filling oxide. The gap filling oxide layer is etched away. A self-sealing oxide layer is deposited overlying the silicon nitride thin layer and the silicon nitride liner layer.

Abstract: A method to make a self-aligned floating gate in a memory device. The method patterns the floating gate (FG) using the trench etch for the shallow trench isolation (STI). Because the floating gate (FG) is adjacent to the raised STI, sharp corners are eliminated between the FG and CG thereby increasing the effectiveness of the intergate dielectric layer. The method includes: forming an first dielectric layer (gate oxide) and a polysilicon layer over a substrate, etching through the first dielectric oxide layer and the polysilicon layer and into the substrate to form a trench. The remaining first dielectric layer and polysilicon layer function as a tunnel dielectric layer and a floating gate. The trench is filled with an isolation layer. The masking layer is removed. An intergate dielectric layer and a control gate are formed over the floating gate and the isolation layer.

Abstract: A method for fabricating a high-density high-capacity capacitor is described. A dielectric layer is provided overlying a semiconductor substrate. A sacrificial layer is deposited overlying the dielectric layer and patterned to form a pattern having a large surface area within a small area on the substrate. In one alternative, spacers are formed on sidewalls of the patterned sacrificial layer. Thereafter, the sacrificial layer is removed. A bottom capacitor plate layer is conformally deposited overlying the spacers. In a second alternative, a bottom capacitor plate layer is deposited overlying the patterned sacrificial layer and etched to leave spacers on sidewalls of the patterned sacrificial layer. Thereafter, the sacrificial layer is removed. In both alternatives, a capacitor dielectric layer is deposited overlying the bottom capacitor plate layer.

Abstract: A method for forming gate structures with smooth sidewalls by amorphizing the polysilicon along the gate boundaries is described. This method results in minimal gate depletion effects and improved critical dimension control in the gates of smaller devices. The method involves providing a gate silicon oxide layer on the surface of the semiconductor substrate. A gate electrode layer, such as polysilicon is deposited over the gate silicon oxide followed by a masking oxide layer deposited over the gate electrode layer. The masking oxide layer is patterned for the formation of the gate electrode. An ion implantation of silicon or germanium amorphizes the area of the polysilicon not protected by the masking oxide mask and also amorphizes the area along the boundaries of the polysilicon gate.

Abstract: A method for forming an L-shaped spacer using a sacrificial organic top coating, then using the L-shaped spacer to simultaneously implant lightly doped source and drain extensions through the L-shaped spacer while implanting source and drain regions beyond the L-shaped spacer. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. In the preferred embodiments, the dielectric spacer layer comprises a silicon nitride layer or a silicon oxynitride layer. A sacrificial organic layer is formed on the dielectric spacer layer. The sacrificial organic layer and the dielectric spacer layer are anisotropically etched to form spacers comprising a triangle-shaped sacrificial organic structure and an L-shaped dielectric spacer. The triangle-shaped sacrificial organic structure is removed leaving an L-shaped dielectric spacer.

Abstract: A method for fabrication of a lightly-doped-drain (LDD) structure for self aligned polysilicon gate MOSFETs is described wherein a polymer layer, formed along the sidewall during the patterning process of the polysilicon gate electrode, is used to mask the source/drain ion implant. The sidewall polymer layer replaces the conventional silicon oxide sidewall as an LDD spacer and offers improved thickness control as well as an improved sequence of processing steps whereby the deposition of a spacer oxide layer onto the gate oxide is eliminated. A cap oxide layer first deposited over the gate polysilicon layer. This oxide layer is then patterned and etched using RIE under conditions which form a polymer sidewall layer along the edges of the cap oxide pattern. The polysilicon layer is then etched, and has a pattern concentric with the cap oxide pattern but wider by the thickness of the polymer sidewall.

Abstract: The present invention provides a method of manufacturing a lightly doped drain (LDD) structure using a polymer layer to define the LDD. The polymer layer is formed in an etch step which defines the gate electrode. The method begins by forming spaced field oxide regions 12 in a substrate 10. Next, a gate oxide layer 14, and a material layer 18 and a hard mask layer 22 are sequentially formed over the active area and the field oxide regions 12. A photo resist block 24 is formed over the hard mask layer 22 over the active area. The hard mask layer 22 is etched using the photo resist block 24 as a mask forming a hard mask block 22. The etch simultaneously forms a polymer layer 26 over the a top and sidewalls of the photo resist block 24 and over the sidewalls of the hard mask block. Impurities ions are implanted into the substrate in the active area using the polymer layer 26 as a mask forming highly doped drain regions 30 in the substrate 10. Next, the photo resist block 24 and the polymer layer 26 are removed.